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DocID024543 Rev 1

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STA380BW

Register description: Sound Terminal compatibility

2.1 channels, two full-b one external full-bridge (OCFG = 10)



FFX1A -> OUT1A



FFX1B -> OUT1B



FFX2A -> OUT2A



FFX2B -> OUT2B



FFX3A -> OUT3A



FFX3B -> OUT3B



EAPD -> OUT4A



TWARN -> OUT4B



FFX1A/1B configured as C1B0 (default: ternary)



FFX2A/2B configured as C2B0 (default: ternary)



FFX3A/3B configured as C3B0 (default: ternary)



FFX4A/4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the
external bridge control signals are muxed.

In this configuration the PWM slot phase is the following as shown in

Figure 40

Figure 40. 2.1 channels (OCFG = 10) PWM slots

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

Obsolete Product(s) - Obsolete Product(s)

Summary of Contents for STA380BW

Page 1: ...20 W into 8 FFXTM 100 dB dynamic range Fixed output PWM frequency at any input sampling frequency Embedded RMS meter for measuring real time loudness New fully programmable noise gating function Up t...

Page 2: ...3 5 Electrical specifications power section 22 3 6 Power on off sequence 24 4 Device overview 25 4 1 Processing data path 25 4 2 Input oversampling 28 4 3 STCompressorTM 28 4 3 1 STC block diagram 29...

Page 3: ...gister addr 0x00 45 6 2 STATUS register addr 0x01 45 6 3 RESET register addr 0x02 46 6 4 Soft volume register addr 0x03 46 6 5 MVOL register addr 0x04 47 6 6 FINEVOL register addr 0x05 47 6 7 CH1VOL r...

Page 4: ...64 6 17 1 Invalid input detect mute enable 64 6 17 2 Binary output mode clock loss detection 64 6 17 3 LRCK double trigger protection 65 6 17 4 Power down 65 6 17 5 External amplifier power down 65 6...

Page 5: ...icient b2 data register bits 23 16 78 6 23 6 Coefficient b2 data register bits 15 8 78 6 23 7 Coefficient b2 data register bits 7 0 78 6 23 8 Coefficient a1 data register bits 23 16 78 6 23 9 Coeffici...

Page 6: ...guration register address 0x6B 0x6C 95 6 33 Coefficient RAM CRC protection address 0x71 0x7D 96 6 34 MISC4 address 0x7E 98 7 Register description Sound Terminal compatibility 100 7 1 Configuration reg...

Page 7: ...7 7 3 Channel 1 volume 120 7 7 4 Channel 2 volume 120 7 7 5 Channel 3 line output volume 120 7 8 Audio preset registers addr 0x0C 122 7 8 1 Audio preset register addr 0x0C 122 7 8 2 AM interference fr...

Page 8: ...fficient a1 data register bits 7 0 132 7 12 11 Coefficient a2 data register bits 23 16 132 7 12 12 Coefficient a2 data register bits 15 8 133 7 12 13 Coefficient a2 data register bits 7 0 133 7 12 14...

Page 9: ...l amplifier hardware pin enabler LPDP LPD LPDE bits address 0x4C bit D7 D6 D5 149 7 22 5 Power down delay selector PNDLSL 2 0 bits address 0x4C bit D4 D3 D2 150 7 22 6 Short circuit check enable bit a...

Page 10: ...PER configuration selection 49 Table 25 FUNCT register 55 Table 26 Master clock select 57 Table 27 Input sampling rates 57 Table 28 Internal interpolation ratio 58 Table 29 IR bit settings as a functi...

Page 11: ...ter release threshold as a function of LxRT bits DRC mode 76 Table 72 RAM block for biquads mixing scaling and bass management 83 Table 73 Extended post scale range 84 Table 74 Extended attack rate li...

Page 12: ...Channel volume as a function of CxVOL 7 0 121 Table 130 AM interference frequency switching bits 122 Table 131 Audio preset AM switching frequency selection 122 Table 132 Bass management crossover 12...

Page 13: ...146 Table 163 PLL register 0x46 bits 146 Table 164 Coefficients extended range configuration 148 Table 165 External amplifier enabler configuration bits 149 Table 166 PNDLSL bits configuration 150 Ta...

Page 14: ...nnels OPER 00 PWM slots 52 Figure 24 2 1 channels OPER 11 PWM slots 53 Figure 25 2 1 channels OPER 10 PWM slots 54 Figure 26 B2 DRC scheme 55 Figure 27 Basic limiter and volume flow diagram 74 Figure...

Page 15: ...gured via digital control to operate in different modes A 2 1 channel setup can be implemented with two half bridges L R together with a single full bridge subwoofer Alternatively the 2 0 channel setu...

Page 16: ...Description STA380BW 16 162 DocID024543 Rev 1 1 1 Block diagram Figure 1 Block diagram STA380BW Obsolete Product s Obsolete Product s...

Page 17: ...D1 10 OUT1A 11 VDD_REG 12 GND_REG 36 35 34 33 32 31 30 29 28 27 26 25 MCLK AGND_PLL VREG_FILT TWARN FFX4A EAPD FFX4B FFX3B FFX3A GND_DIG1 VDD_DIG1 GND N C GND 13 N C 14 N C 15 N C 16 GND 17 GND 18 N C...

Page 18: ...reg ground 13 14 15 18 19 23 24 26 N C Not connected 28 VDDDIG1 POWER I O ring power supply 29 GNDDIG1 POWER Digital core ground 30 FFX3A OUTPUT Digital PWM line out 31 FFX3B OUTPUT Digital PWM line o...

Page 19: ...ection pins must be connected to GND 46 TEST_MODE INPUT This pin must be connected to ground pull down 47 GNDDIG2 POWER Digital I O ground 48 VDDDIG2 POWER Digital core LDO supply 16 17 20 22 25 27 GN...

Page 20: ...nditions may rise beyond the maximum operating conditions for a short time when no or very low current is sunk amplifier in mute state In this case the reliability of the device is guaranteed provided...

Page 21: ...6 V VDD_DIG Digital supply voltage 2 7 3 3 3 6 V Tamb Ambient temperature 0 70 C Table 6 Electrical specifications digital section Symbol Parameter Conditions Min Typ Max Unit Iil Low level input curr...

Page 22: ...ise time Resistive load 2 10 18 ns tf Fall time Resistive load 2 10 18 ns Ivcc Supply current from Vcc in power down PWRDN 0 0 1 1 A Supply current from Vcc in operation PCM Input signal 60 dBfs Switc...

Page 23: ...DocID024543 Rev 1 23 162 STA380BW Electrical specifications Figure 3 Test circuit Obsolete Product s Obsolete Product s...

Page 24: ...CMD0 CMD1 CMD2 Don t care Don t care CMD0 CMD1 CMD2 Don t care Don t care Don t care CMD0 CMD1 CMD2 Don t care Don t care CMD0 CMD1 CMD2 Don t care Don t care CMD0 CMD1 CMD2 Don t care Note no specifi...

Page 25: ...s per channel are enabled plus the pre configured Bass and Treble controls BQL 0 BQ5 0 BQ6 0 BQ7 0 The STA380BW offers the possibility to share the filter coefficients between the two processing chann...

Page 26: ...e used to perform LFE This configuration and features ensure the backward compatibility with previous Sound Terminal products Figure 7 Processing path second part 2 1 output with individually configur...

Page 27: ...10 biquad filters are available for dedicated processing Please refer to Section 4 3 STCompressorTM for further information about this feature Figure 9 Processing path second part 2 1 output configura...

Page 28: ...ing block is running at 96 kHz It is not recommended to use the x3 oversampling feature when Fs 32 kHz because of the PLL maximum frequency constraint 4 3 STCompressorTM The STCompressorTM STC from no...

Page 29: ...er 4 1 Processing data path please refer to the appropriate paragraphs and registers 4 3 2 Band splitter The band splitter block is used to divide the signal into 2 sub bands typically low and high fr...

Page 30: ...l in dB Two kinds of measures are performed peak and RMS The mapper configuration and the input signal automatically determine which measurement to take into account 4 3 4 Mapper The mapper block comp...

Page 31: ...ld which represents the maximum output power allowed The signal is limited to avoid unpredictable effects and damages The compressor threshold the limiter threshold and the compressor rate are all use...

Page 32: ...ior as a limiter Table 9 Compressor ratio Compressor ratio Ratio value 0 1 1 1 1 1 25 2 1 1 5 3 1 1 75 4 1 2 5 1 2 5 6 1 3 7 1 3 5 8 1 4 9 1 4 5 10 1 5 11 1 5 5 12 1 6 13 1 7 14 1 8 15 1 16 INPUT L T...

Page 33: ...owing equation The release rate is user selectable and its range is 0 0078 1 dB ms with a 0 0039 dB ms step 4 3 6 Dynamic attack Due to its dynamic the input signal may exceed the limiter threshold by...

Page 34: ...llify the STC effect Each sub band has its own and independent offset Its range is 0 48 dB with a 0 25 dB step Table 11 Figure 14 Offset effect 4 3 8 Stereo link The stereo link feature allows applyin...

Page 35: ...ffDecValue 0 where CoeffI2CValue is the final decimal value to be converted into hexadecimal notation while CoeffDecValue is the coefficient value in decimal notation to start from Output Ch 0 Attenua...

Page 36: ...ample Original value dec I2 C value hex 48 00 0x600000 24 00 0x300000 16 00 0x200000 12 00 0x180000 06 00 0x0C0000 02 00 0x040000 01 00 0x020000 01 00 0xFE0000 02 00 0xFC0000 06 00 0xF40000 12 00 0xE8...

Page 37: ...16 0 25 dB ms 0x200000 0x5B LT limiter threshold 24 12 0 25 dB 0x000000 0x5C CR compressor ratio 0 15 1 index 0x000000 0x5D CT compressor threshold 48 0 0 25 dB 0x000000 CH1 Band 0 DRC 2 0x5E RR relea...

Page 38: ...0x45 B1 2 1 1 2 2 4 4 0x000000 0x46 B2 1 1 2 2 4 4 0x000000 0x47 A1 2 1 1 2 2 4 4 0x000000 0x48 A2 1 1 2 2 4 4 0x000000 0x49 B0 2 1 1 2 2 4 4 0x100000 Band 1 BQ0 0x4A B1 2 1 1 2 2 4 4 0x000000 0x4B B2...

Page 39: ...on of the data bus SDA signal while the clock signal SCL is stable in the high state A START condition must precede any command for data transfer 5 1 3 Stop condition STOP is identified by a low to hi...

Page 40: ...by sending one byte of data The master then terminates the transfer by generating a STOP condition 5 4 2 Current address multi byte read The multi byte read modes can start from any internal address S...

Page 41: ...AD DEV ADDR ACK START RW SUB ADDR ACK DEV ADDR ACK STOP RANDOM ADDRESS READ DATA NO ACK W R T R A T S DEV ADDR ACK START DATA ACK DATA ACK STOP SEQUENTIAL CURRENT READ DATA NO ACK DEV ADDR ACK START R...

Page 42: ...map table NEW MAP Addr Name D7 D6 D5 D4 D3 D2 D1 D0 0x00 CLK CLK_CFG 3 0 I2S 0x01 STATUS FAULT DRCCRC EQCRC BADPWM I2SERR PLLUL 0x02 RESET SRESET 0x03 SVOL SVOL 1 0 0x04 MVOL MVOL 7 0 0x05 FINEVOL FIN...

Page 43: ...C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16 0x32 A2CF2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8 0x33 A2CF3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0 0x34 B0CF1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B...

Page 44: ...0 7 0 0x63 ZCCFG2 RMS_CH0 15 8 0x64 ZCCFG3 RMS_CH1 7 0 0x65 ZCCFG4 RMS_CH1 15 8 0x6B STCCFG0 NP_ CRCRES 0x6C STCCFG1 STC_LNK 0x6F MTH0 MTH 7 0 0x71 BQCHKE0 BQ_CKE 7 0 0x72 BQCHKE1 BQ_CKE 15 8 0x73 BQC...

Page 45: ...depends on CONFB register status D7 D6 D5 D4 D3 D2 D1 D0 FAULT DRCCRC EQCRC BADPWM Reserved Reserved I2SERR PLLUL NA NA NA NA NA NA NA NA Table 15 STATUS register Bit R W RST Name Description 7 R FAUL...

Page 46: ...48 kHz 96 kHz or 192 kHz D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved SRESET 0 0 0 0 0 0 0 0 Table 16 RESET register Bit R W RST Name Description 0 R W 0 SRES...

Page 47: ...itchoff 0x01 Mute 0x02 Mute PWM on 0x03 Mute PWM on others volume MVOL 255 2 dB 1 1 If the volume is below 60 dB the level will be approximated to 1 dB step 6 R W 0 5 R W 0 4 R W 0 3 R W 0 2 R W 0 1 R...

Page 48: ...1VOL 159 2 dB 1 1 If the volume is below 60 dB the level will be approximated to 1 dB step 6 R W 0 5 R W 0 4 R W 1 3 R W 1 2 R W 1 1 R W 1 0 R W 1 D7 D6 D5 D4 D3 D2 D1 D0 CH2VOL 7 0 1 0 0 1 1 1 1 1 Ta...

Page 49: ...R configuration selection OPER 1 0 Output configuration PBTL enable 00 2 channel full bridge power 2 channel data out 1A 1B 1A 1B 2A 2B 2A 2B LineOut1 3A 3B LineOut2 4A 4B Line out configuration deter...

Page 50: ...el 1 LPF LineOut1 OUT3B LPF LineOut2 OUT4B OUT4A OUT3A Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 3 Channel 1 Channel 2 Half Bridge Half Bridge Half Bridge Half Br...

Page 51: ...X1 B FFX2 A FFX 2B OUT1A OUT1B OUT2A OUT2B Power Bridge OUT1A OUT1B OUT2A OUT2B FFX3 A FFX3B FFX4 A FFX 4B OUT3A OUT3B OUT4A OUT4B FFX modulator REMAP FFX1A FFX1 B FFX2 A FFX 2B OUT1A OUT1B OUT2A OUT2...

Page 52: ...ured as line out ternary FFX4A 4B configured as line out ternary On channel 3 line out LOC bits 00 reg 0x17 bit D7 D6 the same data as channel 1 processing is sent On channel 4 line out LOC bits 00 th...

Page 53: ...on channel 3 has full control volume EQ etc On OUT3 OUT4 channels channel 1 and channel 2 PWM are replicated In this configuration the PWM slot phase is the following as shown in Figure 24 Figure 24 2...

Page 54: ...y FFX3A 3B configured as ternary FFX4A 4B is not used In this configuration channel 3 has full control volume EQ etc On OUT4 channel the external bridge control signals are muxed In this configuration...

Page 55: ...PEQ PEQ Reserved AMDRC MDRCE DRC 0 0 1 0 0 0 0 0 Table 25 FUNCT register Bit R W RST Name Description 6 R W 0 CRC 0 disable CRC computation and comparison 1 enable CRC computation and comparison 5 R W...

Page 56: ...31 For the user programmable mode use the formulas below to compute the high pass filters where alpha 1 sin 0 cos 0 and 0 is the cutoff frequency A first order filter is recommended to guarantee that...

Page 57: ...er bits The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally In Table 27 MCS 111 and 110 indicate that BICKI has to be...

Page 58: ...o 0 which directs the power output block to begin recovery holds it at 0 for period of time in the range of 0 1 ms to 1 second as defined by the fault detect recovery constant register FDRC registers...

Page 59: ...ts are shown in the tables that follow 6 13 2 Serial data first bit D7 D6 D5 D4 D3 D2 D1 D0 C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0 1 0 0 0 0 0 0 0 Table 31 Serial data first bit SAIFB Format 0 MSB...

Page 60: ...ormats for LSB first SAIFB 1 BICKI SAI 3 0 SAIFB Interface format 32 fs 1100 1 I2 S 15 bit data 1110 1 Left right justified 16 bit data 48 fs 0100 1 I2 S 23 bit data 0100 1 I2 S 20 bit data 1000 1 I2...

Page 61: ...ocessing channel 6 14 Configuration register C addr 0x13 6 14 1 FFX compensating pulse size register Table 34 Delay serial clock enable Bit R W RST Name Description 5 R W 0 DSCKE 0 No serial clock del...

Page 62: ...y EQ updates only have to be performed once Table 37 Compensating pulse size CSZ 3 0 Compensating pulse size 0000 0 ns 0 ticks compensating pulse size 0001 20 ns 1 tick clock period compensating pulse...

Page 63: ...ed to approximately 83 dB in this mode which is still greater than the SNR of AM radio Table 41 Zero detect mute enable Bit R W RST Name Description 6 R W 0 ZDE Setting of 1 enables the automatic zero...

Page 64: ...put 50 duty cycle Table 45 PWM speed mode Bit R W RST Name Description 4 R W 0 PWMS 0 Normal speed 384 kHz all channels 1 Odd speed 341 3 kHz all channels Not suitable for binary BTL mode Table 46 Zer...

Page 65: ...preserved once the device recovers from power down 6 17 5 External amplifier power down The EAPD register directly disables enables the internal power circuitry When EAPD 0 the internal power section...

Page 66: ...output fixed no volume no EQ 01 Line output variable CH3 volume effects line output no EQ 10 Line output variable with EQ CH3 volume effects line output 11 Reserved Table 53 Mute configuration Bit R W...

Page 67: ...approximately 96 kHz A hard instantaneous mute can be obtained by programming a value of 0xFF 255 to any channel volume register or the master volume register When volume offsets are provided via the...

Page 68: ...uency selection AMAM 2 0 48 kHz 96 kHz input fs 44 1 kHz 88 2 kHz input fs 000 0 535 MHz 0 720 MHz 0 535 MHz 0 670 MHz 001 0 721 MHz 0 900 MHz 0 671 MHz 0 800 MHz 010 0 901 MHz 1 100 MHz 0 801 MHz 1 0...

Page 69: ...0100 140 Hz 0101 160 Hz 0110 180 Hz 0111 200 Hz 1000 220 Hz 1001 240 Hz 1010 260 Hz 1011 280 Hz 1100 300 Hz 1101 320 Hz 1110 340 Hz 1111 360 Hz D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Rese...

Page 70: ...ream In this mode output A of a channel is considered the positive output and output B is the negative inverse 6 20 5 Limiter select Limiter selection can be made on a per channel basis according to t...

Page 71: ...21 Tone control register addr 0x22 6 21 1 Tone control Table 64 Channel output mapping as a function of C3OM bits C3OM 1 0 Channel x output source from 00 Channel1 01 Channel 2 10 Channel 3 D7 D6 D5...

Page 72: ...nnels in unison The limiter attack thresholds are determined by the LxAT registers if the EATHx 7 bit D7 of register 0x43 or 0x45 bits are set to 0 else the thresholds are determined by EATHx 6 0 It i...

Page 73: ...the release rate register The gain can never be increased past its set value and therefore the release only occurs if the limiter has already reduced the gain The release threshold value can be used...

Page 74: ...Slow 0000 0 5116 Fast Slow 0001 2 7072 0001 0 1370 0010 2 2560 0010 0 0744 0011 1 8048 0011 0 0499 0100 1 3536 0100 0 0360 0101 0 9024 0101 0 0299 0110 0 4512 0110 0 0264 0111 0 2256 0111 0 0208 1000...

Page 75: ...n of LxRT bits AC mode LxAT 3 0 AC dB relative to fs LxRT 3 0 AC dB relative to fs 0000 12 0000 0001 10 0001 29 dB 0010 8 0010 20 dB 0011 6 0011 16 dB 0100 4 0100 14 dB 0101 2 0101 12 dB 0110 0 0110 1...

Page 76: ...ld as a function of LxAT bits DRC mode Table 71 Limiter release threshold as a function of LxRT bits DRC mode LxAT 3 0 DRC dB relative to volume LxRT 3 0 DRC dB relative to volume LxAT 0000 31 0000 00...

Page 77: ...ers addr 0x27 0x37 6 23 1 Coefficient address register 6 23 2 Coefficient b1 data register bits 23 16 6 23 3 Coefficient b1 data register bits 15 8 6 23 4 Coefficient b1 data register bits 7 0 D7 D6 D...

Page 78: ...C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2B7 C2B6 C2B5 C2B4 C2B3...

Page 79: ...oefficient base address five sets of three store the values of the 24 bit coefficients to be written or that were read and one contains bits used to control the write read of the coefficient s to from...

Page 80: ...C address 0x2C 8 Read the bottom 8 bits of coefficient b2 in I2 C address 0x2D 9 Read the top 8 bits of coefficient a1 in I2 C address 0x2E 10 Read the middle 8 bits of coefficient a1 in I2 C address...

Page 81: ...11 Write the top 8 bits of coefficient a2 in I2 C address 0x31 12 Write the middle 8 bits of coefficient a2 in I2 C address 0x32 13 Write the bottom 8 bits of coefficient a2 in I2 C address 0x33 14 Wr...

Page 82: ...range 4 4 Xover filters use only the standard coefficients range 1 1 By default all user defined filters are pass through where all coefficients are set to 0 except the channel 1 and 2 b0 2 coefficien...

Page 83: ...2nd order filter for XO 000 C12H0 b1 2 0x000000 41 0x29 C12H1 b2 0x000000 42 0x2A C12H2 a1 2 0x000000 43 0x2B C12H3 a2 0x000000 44 0x2C C12H4 b0 2 0x400000 45 0x2D Channel 3 Biquad for XO 000 Low pass...

Page 84: ...set to 1 a 48 dB offset is applied to the coefficient RAM value so post scale can act as a gain too 6 25 2 Extended attack rate The attack rate shown in Table 67 can be extended to provide up to an 8...

Page 85: ...its are ignored if BQL 0 or if DEMP 1 relevant for BQ5 or CxTCB 1 relevant for BQ6 and BQ7 Table 75 Extended attack rate limiter 2 XAR2 Mode 0 Limiter2 attack rate is configured using Table 67 1 Limit...

Page 86: ...ency from the pad D7 D6 D5 D4 D3 D2 D1 D0 PLL_FRAC 15 8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 PLL_FRAC 7 0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 PLL_DITH 1 0 PLL_NDIV 5 0 0 0 0 0 0 0 0 0 D7 D6 D5...

Page 87: ...integer ratio 1 PLL use fractional ratio 5 R W 0 PLL_STB PLL synchronous divider changes strobe 4 R W 0 PLL_STBBYP 0 PLL_STB is active 1 PLL_STB control is bypassed 3 R W 0 PLL_IDIV 3 0 Input PLL divi...

Page 88: ...means that OUTxx is shorted to Vcc finally OUTSH 0 means that OUT1B is shorted to OUT2A To be noted that once the check is performed and the tristate released the short protection is not active anymor...

Page 89: ...ted by dotted lines in the figure If one of the three tests or all fail the power bridge outputs are kept in the tristate until the procedure is restarted with a new EAPD toggling In this figure EAPD...

Page 90: ...cycles PLL internal frequency the bridge is put in power down tristate mode There is also the possibility to change this behavior so that the power bridge will be switched off immediately after the P...

Page 91: ...and in case of power down assertion pin 42 is tied to LPDP The LPDP bit when set negates the value programmed as the LPD value refer to the following table Figure 29 Alternate function for INTLINE pi...

Page 92: ...measured PWM duty cycle is detected greater than or equal to TH for more than BPTIM PWM periods the corresponding PWM bit will be set in register 0x01 In case of binary modulation there are two thresh...

Page 93: ...level is detected greater than threshold hysteresis The measured level is then reported for each input channel on registers ZCCCFG1 ZCCCFG2 ZCCCFG3 ZCCCFG4 according to the following equation Value_i...

Page 94: ...at any write operation to the MTH bits will set the low threshold If the zero mute block does not detect mute it will mute the output when the current RMS value falls below the low threshold If the ze...

Page 95: ...ES Reserved Reserved 0 0 0 1 0 0 0 0 Table 91 STCCFG0 register Bit R W RST Name Description 2 R W 0 CRC_RES 0 CRC comparison successful 1 CRC comparison error D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved...

Page 96: ...0 XCCKE 23 XCCKE 22 XCCKE 21 XCCKE 20 XCCKE 19 XCCKE 18 XCCKE 17 XCCKE 16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 BQCKR 7 BQCKR 6 BQCKR 5 BQCKR 4 BQCKR 3 BQCKR 2 BQCKR 1 BQCKR 0 0 0 0 0 0 0 0 0 D7 D6...

Page 97: ...omatic reset activation is the following Download the set of coefficients RAM locations 0x00 0x27 Download the externally computed biquad checksum into registers BQCHKR Enable the checksum of the biqu...

Page 98: ...x27 0x37 Direct access is implemented as follows D7 D6 D5 D4 D3 D2 D1 D0 SMAP reserved reserved reserved reserved reserved WRA CH12 1 0 0 0 0 0 0 0 Table 94 Misc register 4 Bit R W RST Name Descriptio...

Page 99: ...efficients direct access multiple write operation Direct single read procedure 1 Set reg 0x7E bit 0 to 1 and bit 1 to 0 to enable the direct RAM access in single read mode 2 Read the coefficient value...

Page 100: ...AUTO XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME 0E C1CFG C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB 0F C2CFG C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB 10 C3CFG C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3V...

Page 101: ...2E MTH2 MTH 21 16 2F MTH1 MTH 15 8 31 EQCFG XOB 32 EATH1 EATHEN1 EATH1 6 0 33 ERTH1 ERTHEN1 ERTH1 6 0 34 EATH2 EATHEN2 EATH2 6 0 35 ERTH2 ERTHEN2 ERTH2 6 0 36 CONFX MDRCE PS48DB XAR1 XAR2 BQ5 BQ6 BQ7...

Page 102: ...5A STCCFG0 LIM_ BYP STC_BYP STC_ENA NP_ CRCRES NP_CRC_ GO 5B STCCFG1 STC_LNK BRC_EN 5E MTH0 MTH 7 0 5F CHPSINC CHPI INITCNT 3 0 CHPRD 60 BQCHKE0 BQ_CKE 7 0 61 BQCHKE1 BQ_CKE 15 8 62 BQCHKE2 BQ_CKE 23...

Page 103: ...e register bits The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally In Table 98 MCS 111 and 110 indicate that BICKI ha...

Page 104: ...0 which directs the power output block to begin recovery holds it at 0 for period of time in the range of 0 1 ms to 1 second as defined by the fault detect recovery constant register FDRC registers 0x...

Page 105: ...l clock BICKI and serial data 1 and 2 SDI12 The SAI bits D3 to D0 and the SAIFB bit D4 are used to specify the serial data format The default serial data format is I2 S MSB first Available formats are...

Page 106: ...0000 0 I2 S 16 to 23 bit data 0001 0 Left justified 16 to 24 bit data 0010 0 Right justified 24 bit data 0110 0 Right justified 20 bit data 1010 0 Right justified 18 bit data 1110 0 Right justified 1...

Page 107: ...rial audio input formats for LSB first SAIFB 1 BICKI SAI 3 0 SAIFB Interface format 32 fs 1100 1 I2 S 15 bit data 1110 1 Left right justified 16 bit data 48 fs 0100 1 I2 S 23 bit data 0100 1 I2 S 20 b...

Page 108: ...n be mapped to any internal processing channel via the channel input mapping registers This allows for flexibility in processing The default settings of these registers map each I2 S input channel to...

Page 109: ...ion 2 R W 1 CSZ0 When OM 1 0 11 this register determines the size of the FFX compensating pulse from 0 clock ticks to 15 clock periods 3 R W 1 CSZ1 4 R W 1 CSZ2 5 R W 0 CSZ3 Table 108 Compensating pul...

Page 110: ...rement address 0x50 0x54 0x2E 0x2F and 0x5E 7 4 5 Submix mode enable 7 5 Configuration register E addr 0x04 Table 110 Post scale link Bit R W RST Name Description 3 R W 1 PSL 0 Each channel uses indiv...

Page 111: ...s are audible 7 5 5 Soft volume update enable Table 114 Noise shaper bandwidth selection Bit R W RST Name Description 2 R W 0 NSBW 1 Third order NS 0 Fourth order NS Table 115 AM mode enable Bit R W R...

Page 112: ...G0 Selects the output configuration 1 R W 0 OCFG1 Table 120 Output configuration engine selection OCFG 1 0 Output configuration PBTL enable 00 2 channel full bridge power 2 channel data out 1A 1B 1A 1...

Page 113: ...nel 2 Channel 1 LPF LineOut1 OUT3B LPF LineOut2 OUT4B OUT4A OUT3A Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 3 Channel 1 Channel 2 Half Bridge Half Bridge Half Bri...

Page 114: ...AP FFX1A FFX1 B FFX2 A FFX 2B OUT1A OUT1B OUT2A OUT2B Power Bridge OUT1A OUT1B OUT2A OUT2B FFX3 A FFX3B FFX4 A FFX 4B OUT3A OUT3B OUT4A OUT4B FFX modulator REMAP FFX1A FFX1 B FFX2 A FFX 2B OUT1A OUT1B...

Page 115: ...nary FFX3A 3B configured as C3B0 default ternary line out FFX4A 4B configured as C4B0 default ternary line out On channel 3 line out LOC bits 00 the same data as channel 1 processing is sent On channe...

Page 116: ...configuration channel 3 has full control volume EQ etc On OUT3 OUT4 channels channel 1 and channel 2 PWM are replicated In this configuration the PWM slot phase is the following as shown in Figure 39...

Page 117: ...B0 default ternary FFX3A 3B configured as C3B0 default ternary FFX4A 4B is not used In this configuration channel 3 has full control volume EQ etc On OUT4 channel the external bridge control signals a...

Page 118: ...power stage then the master clock to all internal hardware except the I2 C block is gated This places the IC in a very low power consumption state 7 6 6 External amplifier power down Table 121 Invalid...

Page 119: ...LOC 1 0 Line output configuration 00 Line output fixed no volume no EQ 01 Line output variable CH3 volume effects line output no EQ 10 Line output variable with EQ CH3 volume effects line output 11 Re...

Page 120: ...nd the channel mutes provide a soft mute with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate approximately 96 kHz A hard instantaneous...

Page 121: ...38 dB 11111110 0xFE 127 5 dB 11111111 0xFF Hard master mute Table 129 Channel volume as a function of CxVOL 7 0 CxVOL 7 0 Volume 00000000 0x00 48 dB 00000001 0x01 47 5 dB 00000010 0x02 47 dB 01011111...

Page 122: ...Audio preset AM switching frequency selection AMAM 2 0 48 kHz 96 kHz input fs 44 1 kHz 88 2 kHz input fs 000 0 535 MHz 0 720 MHz 0 535 MHz 0 670 MHz 001 0 721 MHz 0 900 MHz 0 671 MHz 0 800 MHz 010 0...

Page 123: ...0 140 Hz 0101 160 Hz 0110 180 Hz 0111 200 Hz 1000 220 Hz 1001 240 Hz 1010 260 Hz 1011 280 Hz 1100 300 Hz 1101 320 Hz 1110 340 Hz 1111 360 Hz D7 D6 D5 D4 D3 D2 D1 D0 C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VPB...

Page 124: ...put can be set to output a binary PWM stream In this mode output A of a channel is considered the positive output and output B is the negative inverse 7 9 5 Limiter select Limiter selection can be mad...

Page 125: ...outputs 7 10 Tone control register addr 0x11 7 10 1 Tone control Table 139 Channel output mapping as a function of CxOM bits CxOM 1 0 Channel x output source from 00 Channel1 01 Channel 2 10 Channel 3...

Page 126: ...needed adjusts the gain of the mapped channels in unison The limiter attack thresholds are determined by the LxAT registers if the EATHx 7 bits are set to 0 else the thresholds are determined by EATH...

Page 127: ...ent upon the release rate register The gain can never be increased past its set value and therefore the release only occurs if the limiter has already reduced the gain The release threshold value can...

Page 128: ...3 1584 Fast Slow 0000 0 5116 Fast Slow 0001 2 7072 0001 0 1370 0010 2 2560 0010 0 0744 0011 1 8048 0011 0 0499 0100 1 3536 0100 0 0360 0101 0 9024 0101 0 0299 0110 0 4512 0110 0 0264 0111 0 2256 0111...

Page 129: ...as a function of LxRT bits AC mode LxAT 3 0 AC dB relative to fs LxRT 3 0 AC dB relative to fs 0000 12 0000 0001 10 0001 29 dB 0010 8 0010 20 dB 0011 6 0011 16 dB 0100 4 0100 14 dB 0101 2 0101 12 dB 0...

Page 130: ...of LxAT bits DRC mode Table 146 Limiter release threshold as a function of LxRT bits DRC mode LxAT 3 0 DRC dB relative to volume LxRT 3 0 DRC db relative to volume LxAT 0000 31 0000 0001 29 0001 38 dB...

Page 131: ...se threshold step is 0 125 dB in the range 12 dB to 0 dB 7 12 User defined coefficient control registers addr 0x16 0x26 7 12 1 Coefficient address register 7 12 2 Coefficient b1 data register bits 23...

Page 132: ...C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C...

Page 133: ...s function One contains a coefficient base address five sets of three store the values of the 24 bit coefficients to be written or that were read and one contains bits used to control the write read o...

Page 134: ...t b2 in I2 C address 0x1B 8 Read the bottom 8 bits of coefficient b2 in I2 C address 0x1C 9 Read the top 8 bits of coefficient a1 in I2 C address 0x1D 10 Read the middle 8 bits of coefficient a1 in I2...

Page 135: ...dress 0x1F 11 Write the top 8 bits of coefficient a2 in I2 C address 0x20 12 Write the middle 8 bits of coefficient a2 in I2 C address 0x21 13 Write the bottom 8 bits of coefficient a2 in I2 C address...

Page 136: ...efficient range 4 4 Xover filters use only the standard coefficients range 1 1 By default all user defined filters are pass through where all coefficients are set to 0 except the channel 1 and 2 b0 2...

Page 137: ...0 High pass 1st order filter for XO 000 C12H0 b1 2 0x000000 41 0x29 C12H1 b2 0x000000 42 0x2A C12H2 a1 2 0x000000 43 0x2B C12H3 a2 0x000000 44 0x2C C12H4 b0 2 0x400000 45 0x2D Channel 3 Biquad for XO...

Page 138: ...cked 7 15 EQ coefficients configuration register addr 0x31 The XOB bit can be used to bypass the crossover filters Logic 1 means that the function is not active In this case the high pass crossover fi...

Page 139: ...high frequency components while limiter 2 DRC2 is used to control the low frequency components see Chapter 7 11 The cutoff frequency of the high pass filters can be user defined XO 3 0 0 or selected f...

Page 140: ...bination For second order filters it is not possible to give a closed formula to get the best coefficients but empirical adjustment should be done DRC settings The DRC blocks used by B2 DRC are the sa...

Page 141: ...BQx bits are ignored if BQL 0 or if DEMP 1 relevant for BQ5 or CxTCB 1 relevant for BQ6 and BQ7 Table 150 Extended attack rate limiter 1 XAR1 Mode 0 Limiter1 attack rate is configured using Table 142...

Page 142: ...n rate is defined by the SVDW 4 0 bits according to the following formula volume down rate 48 N 1 dB ms where N is the SVDW 4 0 value Note For volume down rates greater than 6 dB msec it is recommende...

Page 143: ...will be defined only by the CxVol registers Fine tuning steps can be set according to the following table for channels 1 2 3 and master volume D7 D6 D5 D4 D3 D2 D1 D0 VRESEN VRESTG C3VR 1 C3VR 0 C2VR...

Page 144: ...he user a manual PLL configuration can be used setting PLL_DIRP to 1 Table 158 Extra volume resolution enable VRESEN VRESTG Mode 0 0 Extra volume resolution disabled 0 1 Extra volume resolution disabl...

Page 145: ...ng enabled rectangular 11 Reserved 6 R W 0 5 R W 0 NDIV PLL loop divider 4 R W 0 3 R W 0 2 R W 0 1 R W 0 0 R W 0 Table 161 PLL register 0x44 bits Bit R W RST Name Description 7 R W 0 PLL_DPD 0 any PLL...

Page 146: ...VCCSH means that OUTxx is shorted to Vcc finally OUTSH 0 means that OUT1B is shorted to OUT2A Table 162 PLL register 0x45 bits Bit R W RST Name Description 5 R W 0 PLL_DIRP 0 PLL configuration is det...

Page 147: ...s to indicate that the bits are carrying the status of the previous EAPD 0 1 toggling to be noted that after reset this state is meaningless since no EAPD transition occurs GND related SHOK bits are u...

Page 148: ...lity of this feature maintaining the 1 1 range unchanged 7 22 Miscellaneous registers address 0x4B 0x4C 7 22 1 Rate power down enable RPDNEN bit address 0x4B bit D7 In the STA380BW by default the powe...

Page 149: ...n and not for a power down applied through the IIC interface Refer to Section 7 22 5 if programming a different number of clock cycles is needed 7 22 3 Channel PWM enable CPWMEN bit address 0x4B bit D...

Page 150: ...ng table 7 22 6 Short circuit check enable bit address 0x4C bit D0 This bit when enabled will activate the short circuit checks before any power bridge activation EAPD bit 0 1 See section 7 20 for mor...

Page 151: ...H 2 1 128 100 If the measured PWM duty cycle is detected greater than or equal to TH for more than BPTIM PWM periods the corresponding PWM bit will be set in register 0x4E In case of binary modulation...

Page 152: ...ted when the input level is detected greater than threshold hysteresis The measured level is then reported for each input channel on registers 0x51 0x52 0x53 0x54 according to the following equation V...

Page 153: ...to 1 so that any write operation to the MTH bits will set the low threshold If the zero mute block does not detect mute it will mute the output when the current RMS value falls below the low threshold...

Page 154: ...sed 5 R W 1 STC_BYP 0 STCompressorTM processing activated 1 STCompressorTM is in pass through 4 R W 1 STC_EN 0 STCompressorTM is switched off no configuration is possible in this state 1 STCompressorT...

Page 155: ...D3 D2 D1 D0 XCCKE 23 XCCKE 22 XCCKE 21 XCCKE 20 XCCKE 19 XCCKE 18 XCCKE 17 XCCKE 16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 BQCKR 7 BQCKR 6 BQCKR 5 BQCKR 4 BQCKR 3 BQCKR 2 BQCKR 1 BQCKR 0 0 0 0 0 0 0...

Page 156: ...the automatic reset activation is the following Download the set of coefficients RAM locations 0x00 0x27 Download the externally computed biquad checksum into registers BQCHKR Enable the checksum of t...

Page 157: ...re reset 7 28 MISC4 address 0x7E D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved reserved reserved reserved SRESET reserved reserved 0 0 0 0 0 0 0 0 Table 172 Misc register 3 Bit R W RST Name Description 2...

Page 158: ...o mode Please refer to the application note for all the other schematics for the recommended output configuration Figure 46 Output configuration for stereo BTL mode in filterlight configuration Note F...

Page 159: ...ffers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com...

Page 160: ...ge dimensions Reference mm Min Typ Max A 0 80 0 90 1 00 A1 0 0 05 D 6 90 7 00 7 10 D2 5 65 5 70 5 75 E 6 90 7 00 7 10 E2 5 65 5 70 5 75 b 0 25 0 30 0 35 b1 0 20 0 25 0 30 e pad pitch 0 50 L1 0 05 0 15...

Page 161: ...DocID024543 Rev 1 161 162 STA380BW Revision history 10 Revision history Table 175 Document revision history Date Revision Changes 15 Apr 2013 1 Initial release Obsolete Product s Obsolete Product s...

Page 162: ...HT ST PRODUCTS ARE NOT AUTHORIZED FOR USE IN WEAPONS NOR ARE ST PRODUCTS DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVICES OR SYSTEMS WI...

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