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STA309A

Registers

Doc ID 13855 Rev 4

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7.2.7 Configuration

register G (0x06)

The STA309A features a DDX processing mode that minimizes the amount of noise
generated in frequency range of AM radio. This mode is intended for use when DDX is
operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to
~83 dB in this mode, which is still greater than the SNR of AM radio.

The STA309A features a 2 DDX processing modes that minimize the amount of noise
generated in frequency range of AM radio. This second mode is intended for use when DDX
is operating in a device with an AM tuner active. This mode eliminates the noise-shaper.

Channels 7 and 8 can be configured to be processed and output in such a manner that
headphones can be driven using and appropriate output device. This signal is a differential
3-wire drive called DDX Headphone.

D7

D6

D5

D4

D3

D2

D1

D0

MPCV

DCCV

HPE

AM2E

AME

COD

SID

PWMD

0

0

0

0

0

0

0

0

Table 34.

Register G bit definitions

Bit

RW

RST

Name

Description

0

RW

0

PWMD

PWM output disable:

0: PWM output normal
1: no PWM output

1

RW

0

SID

Serial interface (I

2

S out) disable:

0: I

2

S output normal

1: no I

2

S output

2

RW

0

COD

Clock output disable:

0: clock output normal
1: no clock output

3

RW

0

AME

AM mode enable:

0: normal DDX operation.
1: AM reduction mode DDX operation.

Table 35.

AM2E bit

Bit

RW

RST

Name

Description

4

RW

0

AM2E

AM2 mode enable:

0: normal DDX operation.
1: AM2 reduction mode DDX operation.

Table 36.

HPE bit

Bit

RW

RST

Name

Description

5

RW

0

HPE

DDX headphone enable:

0: channels 7 and 8 normal DDX operation
1: channels 7 and 8 headphone operation

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Summary of Contents for STA309A

Page 1: ...zero detect and invalid input mute Automatic invalid input detect mute Advanced PopFree operation Advanced AM interference frequency switching and noise suppression modes I2S output channel mapping function Independent channel volume and DSP bypass Channel mapping of any input to any processing DDX channel DC blocking selectable high pass filter Selectable per channel DDX damped ternary or binary ...

Page 2: ...ge 16 5 1 2 Start condition 16 5 1 3 Stop condition 16 5 1 4 Data input 16 5 2 Device addressing 16 5 3 Write operation 17 5 3 1 Byte write 17 5 3 2 Multi byte write 17 6 Application reference schematic 18 7 Registers 19 7 1 Register summary 19 7 2 Register description 22 7 2 1 Configuration register A 0x00 22 7 2 2 Configuration register B 0x01 serial input formats 24 7 2 3 Configuration register...

Page 3: ... mute bypass 0x17 36 7 2 25 Channel 6 volume trim mute bypass 0x18 36 7 2 26 Channel 7 volume trim mute bypass 0x19 36 7 2 27 Channel 8 volume trim mute bypass 0x1A 36 7 2 28 Channel input mapping channels 1 and 2 0x1B 38 7 2 29 Channel input mapping channels 3 and 4 0x1C 38 7 2 30 Channel input mapping channels 5 and 6 0x1D 38 7 2 31 Channel input mapping channels 7 and 8 0x1E 38 7 2 32 AUTO1 Aut...

Page 4: ...x3A 54 7 2 61 Coefficient address register 1 0x3B 55 7 2 62 Coefficient address register 2 0x3C 55 7 2 63 Coefficient b1 data register bits 23 16 0x3D 55 7 2 64 Coefficient b1 data register bits 15 8 0x3E 55 7 2 65 Coefficient b1 data register bits 7 0 0x3F 55 7 2 66 Coefficient b2 data register bits 23 16 0x40 55 7 2 67 Coefficient b2 data register bits 15 8 0x41 55 7 2 68 Coefficient b2 data reg...

Page 5: ...cale 60 8 2 Variable max power correction 62 8 2 1 MPCC1 2 0x4D 0x4E 62 8 3 Variable distortion compensation 62 8 3 1 DCC1 2 0x4F 0x50 62 8 4 PSCorrect registers 63 8 4 1 PSC1 2 ripple correction value RCV 0x51 0x52 63 8 4 2 PSC3 correction normalization value CNV 0x53 63 9 Package mechanical data 64 10 Trademarks and other acknowledgements 65 11 Revision history 66 ...

Page 6: ...SAIFB bit 24 Table 17 SAI and SAIFB serial clock 25 Table 18 SAO bits 26 Table 19 SAOFB bit 26 Table 20 SAO serial clock 26 Table 21 OM bits 27 Table 22 Output stage mode 27 Table 23 CSZ bits 27 Table 24 CSZ definition 28 Table 25 MPC bit 28 Table 26 CnBO bits 28 Table 27 HPB bit 29 Table 28 DRC bit 29 Table 29 DEMP bit 29 Table 30 PSL bit 30 Table 31 BQL bit 30 Table 32 PWMS bits 30 Table 33 PWM ...

Page 7: ...AM bits 42 Table 64 XO bits 42 Table 65 PEQ bits 43 Table 66 xGEQ bits 44 Table 67 CnBLP bits 45 Table 68 CnMXLP bits 45 Table 69 CnEQBP bits 46 Table 70 BTC and TTC bits 47 Table 71 Channel limiter mapping 49 Table 72 Attack rate 49 Table 73 Release rate 50 Table 74 LnAT bits anti clipping 50 Table 75 LnRT bits anti clipping 51 Table 76 LnAT bits dynamic range compression 51 Table 77 LnRT bits dy...

Page 8: ... signal flow 9 Figure 3 Pin connection top view 10 Figure 4 Write mode sequence 17 Figure 5 Read mode sequence 17 Figure 6 Reference schematic for STA309A based application 18 Figure 7 Basic limiter and volume flow diagram 49 Figure 8 Channel mixer 60 Figure 9 TQFP64 10 x 10 x 1 4 mm package dimensions 64 ...

Page 9: ...DX 1x 2x 4x Interp Biquads B T Volume Limiter 2x Interp Distortion Compensation NS C_Con PWM DDX Output Interp_Rate 8 Inputs From I2S DSD Conversion 6 Inputs From DSD Mapping Mix 1 DSDE Mix 2 PreScale High Pass Filter Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Biquad 7 Biquad 8 Bass Hard Set to 18dB when AutoMode EQ AMEQ Hard Set Coeffecients when AutoMode EQ AMEQ Hard Set Coeffecients when Auto...

Page 10: ...TTL input buffer LRCKI DSD_2 Input left right clock DSD input channel 2 11 5 V tolerant TTL input buffer BICKI DSD_1 Input serial clock DSD input channel 1 15 5 V tolerant TTL schmitt trigger input buffer RESET Global reset 16 CMOS input buffer with pull down PLL_BYPASS Bypass phase locked loop 1 2 3 5 6 4 7 8 9 10 27 11 28 29 30 31 32 59 58 57 56 54 55 53 52 51 50 49 43 42 41 39 38 40 48 47 46 44...

Page 11: ...TL 16mA output buffer OUT8A PWM channel 8 output A 31 3 3 V capable TTL 16mA output buffer OUT7B PWM channel 7 output B 32 3 3 V capable TTL 16mA output buffer OUT7A PWM channel 7 output A 33 3 3 V capable TTL 16mA output buffer OUT6B PWM channel 6 output B 34 3 3 V capable TTL 16mA output buffer OUT6A PWM channel 6 output A 38 3 3 V capable TTL 16mA output buffer OUT5B PWM channel 5 output B 39 3...

Page 12: ...Output left right clock 57 3 3 V capable TTL 2mA output buffer SDO_12 Output serial data channels 1 2 58 3 3 V capable TTL 2mA output buffer SDO_34 Output serial data channels 3 4 62 3 3 V capable TTL 2mA output buffer SDO_56 Output serial data channels 5 6 63 3 3 V capable TTL 2mA output buffer SDO_78 Output serial data channels 7 8 64 5 V tolerant TTL schmitt trigger input buffer PWDN Device pow...

Page 13: ... power supply pin VDDA 0 5 4 V Vi Voltage on input pins 0 5 VDD 0 5 V Vo Voltage on output pins 0 5 VDD 0 3 V Tstg Storage temperature 40 150 C Tamb Ambient operating temperature 40 90 C Table 4 Thermal data Symbol Parameter Min Typ Max Unit Rthj amb Thermal resistance junction to ambient 85 C W Table 5 Recommended operating condition Symbol Parameter Min Typ Max Unit VDD I O power supply pin VDD ...

Page 14: ...imum after an electrostatic stress on the pin µA Iih High level input no pull down Vi VDD 2 µA IOZ Tristate output leakage without pull up down Vi VDD 2 µA Vesd Electrostatic protection human body model Leakage 1µA 2000 V Table 7 DC electrical characteristics 3 3 V buffers Symbol Parameter Conditions Min Typ Max Unit VIL Low level input voltage 0 8 V VIH High level input voltage 2 0 V VILhyst Low ...

Page 15: ...their defaults I2 C bus The SA SDA and SCL pins operate per the Phillips I2 C specification See Section 5 Phase locked loop PLL The phase locked loop section provides the system timing signals and CKOUT Clock output CKOUT System synchronization and master clocks are provided by the CKOUT PWM outputs OUT1 through OUT8 The PWM outputs provide the input signal for the power devices External amplifier...

Page 16: ...ata transfer 5 1 3 Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state A STOP condition terminates communication between STA309A and the bus master 5 1 4 Data input During the data input the STA309A samples the SDA signal on the rising edge of clock SCL For correct device operation the SDA signal must be stab...

Page 17: ...ledged by the Omega DDX core The master then terminates the transfer by generating a STOP condition 5 3 2 Multi byte write The multi byte write modes can start from any internal address The master generating a STOP condition terminates the transfer Figure 4 Write mode sequence Figure 5 Read mode sequence DEV ADDR ACK START RW SUB ADDR ACK DATA IN ACK STOP BYTE WRITE DEV ADDR ACK START RW SUB ADDR ...

Page 18: ...3 B 7 5 1 B3 1 B 1 287 B 287 B 287 B 287 B 1 B 1 3 5 2 6 2B 6 2B 6 2B 2 1 B 9 B 287 3 1 6 B 5 9 B 1 1 1 1 6 2B 9 B 287 B 287 B 287 B 287 B 287 B 287 B 287 B 287 B 287 B 287 B 287 B 287 B 9 B 7 67B02 1 B 1 9 B 1 B 9 B3 8 67 3 5 1 9 5 5 16 5 16 3 132 1 9 5 RKP PK B B 6 7 6 32 5B21B567 0 6 7 6 7 3 5 6 B 3 5 1 B B B B B B B B 9 B 9 9 9 9 9 9 9 7KH 3 ILOWHU PXVW EH SODFHG DV F DV SRVVLEOH WR WKH 67 SLQ...

Page 19: ...2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 0x0D C3VOL C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0 0x0E C4VOL C4V7 C4V6 C4V5 C4V4 C4V3 C4V2 C4V1 C4V0 0x0F C5VOL C5V7 C5V6 C5V5 C5V4 C5V3 C5V2 C5V1 C5V0 0x10 C6VOL C6V7 C6V6 C6V5 C6V4 C6V3 C6V2 C6V1 C6V0 0x11 C7VOL C7V7 C7V6 C7V5 C7V4 C7V3 C7V2 C7V1 C7V0 0x12 C8VOL C8V7 C8V6 C8V5 C8V4 C8V3 C8V2 C8V1 C8V0 0x13 C1VTMB C1M C1VBP Reserved C1VT4 C1VT3 C1VT2 C1VT1 ...

Page 20: ...3MXLP C2MXLP C1MXLP Processing bypass 0x2A EQBP C8EQBP C7EQBP C6EQBP C5EQBP C4EQBP C3EQBP C2EQBP C1EQBP 0x2B TONEBP C8TCB C7TCB C6TCB C5TCB C4TCB C3TCB C2TCB C1TCB Tone control 0x2C TONE TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 Dynamics control 0x2D C1234LS C4LS1 C4LS0 C3LS1 C3LS0 C2LS1 C2LS0 C1LS1 C1LS0 0x2E C5678LS C8LS1 C8LS0 C7LS1 C7LS0 C6LS1 C6LS0 C5LS1 C5LS0 0x2F L1AR L1A3 L1A2 L1A1 L1A0 L1R3...

Page 21: ...8 C3B17 C3B16 0x44 A1CF2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8 0x45 A1CF3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0 0x46 A2CF1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16 0x47 A2CF2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8 0x48 A2CF3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0 0x49 B0CF1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16 0x4A B0CF2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 ...

Page 22: ... input sample rate is determined by both the MCSn and the IRn input rate register bits The MCSn bits determine the PLL factor generating the internal clock and the IRn bits determine the oversampling ratio used internally 7 6 5 4 3 2 1 0 COS1 COS0 DSPB IR1 IR0 MCS2 MCS1 MCS0 1 0 0 0 0 0 1 1 Table 9 MSC bits Bit RW RST Name Description 0 RW 1 MCS0 Master clock select selects the ratio between the i...

Page 23: ...Name Description 3 RW 0 IR0 Interpolation ratio select selects internal interpolation ratio based on input I2 S sample frequency 4 RW 0 IR1 Table 12 IR sample rates IR 1 0 Input sample rate fs kHz 1st stage interpolation ratio 00 32 4 times oversampling 00 44 1 4 times oversampling 00 48 4 times oversampling 01 88 2 2 times oversampling 01 96 2 times oversampling 10 176 4 Pass through 10 192 Pass ...

Page 24: ...78 pin 6 The SAI SAIFB register Configuration Register B address 0x01 is used to specify the serial data format The default serial data format is I2S MSB first Available formats are shown in the tables and figure that follow Note Serial input and output formats are specified separately For example SAI 1110 and SAIFB 1 would specify right justified 16 bit data LSB first D7 D6 D5 D4 D3 D2 D1 D0 Rese...

Page 25: ...a 0001 X Left justified 24 bit data 0101 X Left justified 20 bit data 1001 X Left justified 18 bit data 1101 X Left justified 16 bit data 0010 X Right justified 24 bit data 0110 X Right justified 20 bit data 1010 X Right justified 18 bit data 1110 X Right justified 16 bit data 64 fs 0000 X I2 S 24 bit data 0100 X I2 S 20 bit data 1000 X I2 S 18 bit data 0000 0 MSB first I2 S 16 bit data 1100 1 LSB...

Page 26: ...ntly from the input format and is done via the SAO and SAOFB bits D7 D6 D5 D4 D3 D2 D1 D0 Reserved SAOFB SAO3 SAO2 SAIO SAO0 0 0 0 0 0 0 0 0 Table 18 SAO bits Bit RW RST Name Description 0 RW 0 SAO0 Serial audio output interface format determines the interface format of the output serial digital audio interface 1 RW 0 SAO1 2 RW 0 SAO2 3 RW 0 SAO3 Table 19 SAOFB bit Bit RW RST Name Description 4 RW...

Page 27: ...Interface data format D7 D6 D5 D4 D3 D2 D1 D0 MPC CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 1 1 0 0 0 0 1 0 Table 21 OM bits Bit RW RST Name Description 0 RW 0 OM0 DDX power output mode selects configuration of DDX output 1 RW 1 OM1 Table 22 Output stage mode OM 1 0 Output stage mode 00 STA50x STA51xB drop compensation 01 Discrete output stage tapered compensation 10 STA50x STA51xB full power mode 11 Varia...

Page 28: ...s negative inverse Table 24 CSZ definition CSZ 4 0 Compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size 11111 31 clock period compensating pulse size Table 25 MPC bit Bit RW RST Name Description 7 RW 1 MPC Max power correction 1 enable STA50x correction for THD reduction near maximum power output D7 D6 D5 D4 D3 D2 D1 D0 C8BO C7BO C6BO C5...

Page 29: ...lume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level By setting this bit to one de emphasis will implemented on all channels When this is used it takes the place of biquad 7 in each channel and any coefficients using biquad 1 will be ignored DSPB DSP bypass bit must be set to 0 for de emphasis to function D7 D6 D5 D4 D3 D2 ...

Page 30: ... once Table 30 PSL bit Bit RW RST Name Description 3 RW 0 PSL Postscale link 0 each channel uses individual postscale value 1 each channel uses channel 1 postscale value Table 31 BQL bit Bit RW RST Name Description 4 RW 0 BQL Biquad link 0 each channel uses coefficient values 1 each channel uses channel 1 coefficient values Table 32 PWMS bits Bit RW RST Name Description 7 5 RW 00 PWMS 2 0 PWM spee...

Page 31: ...cessed and output in such a manner that headphones can be driven using and appropriate output device This signal is a differential 3 wire drive called DDX Headphone D7 D6 D5 D4 D3 D2 D1 D0 MPCV DCCV HPE AM2E AME COD SID PWMD 0 0 0 0 0 0 0 0 Table 34 Register G bit definitions Bit RW RST Name Description 0 RW 0 PWMD PWM output disable 0 PWM output normal 1 no PWM output 1 RW 0 SID Serial interface ...

Page 32: ...CC bits for MPC coefficient D7 D6 D5 D4 D3 D2 D1 D0 ECLE LDTE BCLE IDE ZDE SVE ZCE NSBW 0 1 1 1 1 1 1 0 Table 39 NSBW bit Bit RW RST Name Description 0 RW 0 NSBW Noise shaper bandwidth selection 1 3rd order NS 0 4th order NS Table 40 ZCE bit Bit RW RST Name Description 1 RW 1 ZCE Zero crossing volume enable 1 volume adjustments will only occur at digital zero crossings 0 volume adjustments will oc...

Page 33: ...er down signal EAPD on clock loss detection 7 2 9 Configuration register I 0x08 This feature utilizes an ADC on SDI78 that provides power supply ripple information for correction Registers PSC1 PSC2 PSC3 are utilized in this mode Table 43 IDE bit Bit RW RST Name Description 4 RW 1 IDE Invalid input detect mute enable 1 enable the automatic invalid input detect mute Table 44 BCLE bit Bit RW RST Nam...

Page 34: ...tion 7 RW 0 EAPD External amplifier power down 0 external power stage power down active 1 normal operation D7 D6 D5 D4 D3 D2 D1 D0 Reserved MMUTE 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0 1 1 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0 0 1 1 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 0 1 1 0 0 0 0 0 D7 D6 ...

Page 35: ...C5V3 C5V2 C5V1 C5V0 0 1 1 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C6V7 C6V6 C6V5 C6V4 C6V3 C6V2 C6V1 C6V0 0 1 1 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C7V7 C7V6 C7V5 C7V4 C7V3 C7V2 C7V1 C7V0 0 1 1 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C8V7 C8V6 C8V5 C8V4 C8V3 C8V2 C8V1 C8V0 0 1 1 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C1M C1VBP Reserved C1VT4 C1VT3 C1VT2 C1VT1 C1VT0 0 0 0 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2M C2VBP R...

Page 36: ...ramping down to mute in 8192 samples from the maximum volume setting at the internal processing rate 192 kHz A hard mute can be obtained by commanding a value of 0xFF 255 to any channel volume register or the master volume register When volume offsets are provided via the master volume register any channel that whose total volume is less than 91 dB will be muted All changes in volume take place at...

Page 37: ...nel Table 49 MV bits MV 7 0 Volume offset from channel value 0x00 0 dB 0x01 0 5 dB 0x02 1 dB 0x4C 38 dB 0xFE 127 dB 0xFF Hardware channel mute Table 50 CnV bits CnV 7 0 Volume 0x00 48 dB 0x01 47 5 dB 0x02 47 dB 0x5F 0 5 dB 0x60 0 dB 0x61 0 5 dB 0xFE 79 5 dB 0xFF Hardware channel mute Table 51 CnVT bits CnVT 4 0 Volume 0x00 to 0x06 10 dB 0x07 9 dB 0x0F 1 dB 0x10 0 dB 0x11 1 dB 0x19 9 dB 0x1A to 0x1...

Page 38: ...y to perform crossovers The default settings of these registers map each I2 S input channel to its corresponding processing channel D7 D6 D5 D4 D3 D2 D1 D0 Reserved C2IM2 C2IM1 C2IM0 Reserved C1IM2 C1IM1 C1IM0 0 0 0 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved C4IM2 C4IM1 C4IM0 Reserved C3IM2 C3IM1 C3IM0 0 0 1 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved C6IM2 C6IM1 C6IM0 Reserved C5IM2 C5IM1 C5IM0 0 ...

Page 39: ...Bit RW RST Name Description 1 0 RW 0 AMEQ 1 0 Biquad 2 6 mode is 00 user programmable 01 preset EQ PEQ bits 10 graphic EQ xGEQ bits 11 auto volume controlled loudness curve Table 54 AMV bits Bit RW RST Name Description 3 2 RW 0 AMV 1 0 Automode volume mode MVOL is 00 MVOL 0 5 dB 256 steps standard 01 MVOL auto curve 30 steps 10 MVOL auto curve 40 steps 11 MVOL auto curve 50 steps 6 4 RW 0 AMGC 2 0...

Page 40: ...e different configurations are selected as they would be by the end user The Automode bass management settings utilize channels 1 6 on the Mix 1 engine Channels 1 6 biquad 6 and channels 1 2 on the mix 2 engine in configuration 2 These functions cannot be user programmed while the bass management Automode is active Not all settings are valid as some configurations are unlikely and do not have to b...

Page 41: ...0 160 Hz when using small single driver satellite speakers as the frequency response of these speakers normally are limited to this region 7 2 34 AUTO3 Automode AM prescale bass management scale 0x21 Table 58 CSS and RSS bits Bitfield 10 01 00 CSS center speaker size Off Large Small RSS rear speaker size Off Large Small Table 59 FSS and SUB bits Bitfield 1 0 FSS front speaker size Large Small SUB ...

Page 42: ...fs 000 0 535 MHz 0 720 MHz 0 535 MHz 0 670 MHz 001 0 721 MHz 0 900 MHz 0 671 MHz 0 800 MHz 010 0 901 MHz 1 100 MHz 0 801 MHz 1 000 MHz 011 1 101 MHz 1 300 MHz 1 001 MHz 1 180 MHz 100 1 301 MHz 1 480 MHz 1 181 MHz 1 340 MHz 101 1 481 MHz 1 600 MHz 1 341 MHz 1 500 MHz 110 1 601 MHz 1 700 MHz 1 501 MHz 1 700 MHz D7 D6 D5 D4 D3 D2 D1 D0 XO2 XO1 XO0 PEQ4 PEQ3 PEQ2 PEQ1 PEQ0 1 0 1 0 0 0 0 0 Table 64 XO ...

Page 43: ...rd 01001 Party 01010 Vocal 01011 Hip Hop 01100 Dialog 01101 Bass boost 1 01110 Bass boost 2 01111 Bass boost 3 10000 Loudness 1 10001 Loudness 2 10010 Loudness 3 10011 Loudness 4 10100 Loudness 5 10101 Loudness 6 10110 Loudness 7 10111 Loudness 8 11000 Loudness 9 11001 Loudness 10 11010 Loudness 11 11011 Loudness 12 11100 Loudness 13 11101 Loudness 14 11110 Loudness 15 11111 Loudness 16 ...

Page 44: ...ed AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0 0 0 0 0 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BGEQ4 BGEQ3 BGEQ2 BGEQ1 BGEQ0 0 0 0 0 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Reserved CGEQ4 CGEQ3 CGEQ2 CGEQ1 CGEQ0 0 0 0 0 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Reserved DGEQ4 DGEQ3 DGEQ2 DGEQ1 DGEQ0 0 0 0 0 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Reserved EGEQ4 EGEQ3 EGEQ2 EGEQ1 EGEQ0 0 0 0 0 1 1 1 1 Table 66 xGEQ bits xGEQ 4 0 Boost c...

Page 45: ...n come from the outputs of the interpolation block as normally occurs CnMXLP 0 or they can come from the outputs of the Mix 2 block This enables the use of additional filtering after the second mix block at the expense of losing this processing capability on the channel D7 D6 D5 D4 D3 D2 D1 D0 C8BLP C7BLP C6BLP C5BLP C4BLP C3BLP C2BLP C1BLP 0 0 0 0 0 0 0 0 Table 67 CnBLP bits Bit RW RST Name Descr...

Page 46: ... Tone control bass treble can be bypassed on a per channel basis If tone control is bypassed on a given channel the two filters that tone control utilizes are made available as user programmable biquads 9 and 10 D7 D6 D5 D4 D3 D2 D1 D0 C8EQBP C7EQBP C6EQBP C5EQBP C4EQCBP C3EQBP C2EQBP C1EQBP 0 0 0 0 0 0 0 0 Table 69 CnEQBP bits Bit RW RST Name Description 7 0 RW 0 CnEQBP For n 1 to 8 0 perform EQ ...

Page 47: ...D6 D5 D4 D3 D2 D1 D0 TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 0 1 1 1 0 1 1 1 Table 70 BTC and TTC bits BTC 3 0 TTC 3 0 Boost cut 0000 12 dB 0001 12 dB 0111 4 dB 0110 2 dB 0111 0 dB 1000 2 dB 1001 4 dB 1101 12 dB 1110 12 dB 1111 12dB D7 D6 D5 D4 D3 D2 D1 D0 C4LS1 C4LS0 C3LS1 C3LS0 C2LS1 C2LS0 C1LS1 C1LS0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C8LS1 C8LS0 C7LS1 C7LS0 C6LS1 C6LS0 C5LS1 C5LS0 0 0 0 0...

Page 48: ...r LnAT setting when this occurs the limiter when active will automatically start reducing the gain The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter The gain reduction occurs on a peak detect algorithm The release of limiter when the gain is again increased is dependent on a RMS detect algorithm The outpu...

Page 49: ... 0 Channel limiter mapping 00 Channel has limiting disabled 01 Channel is mapped to limiter 1 10 Channel is mapped to limiter 2 Table 72 Attack rate LnA 3 0 Attack rate dB ms 0000 3 1584 fast 0001 2 7072 0010 2 2560 0011 1 8048 0100 1 3536 0101 0 9024 0110 0 4512 0111 0 2256 1000 0 1504 1001 0 1123 1010 0 0902 1011 0 0752 1100 0 0645 1101 0 0564 1110 0 0501 1111 0 0451 slow Gain Attenuation Satura...

Page 50: ...99 0100 0 0360 0101 0 0299 0110 0 0264 0111 0 0208 1000 0 0198 1001 0 0172 1010 0 0147 1011 0 0137 1100 0 0134 1101 0 0117 1110 0 0110 1111 0 0104 slow Table 74 LnAT bits anti clipping LnAT 3 0 Anti clipping AC dB relative to FS 0000 12 0001 10 0010 8 0011 6 0100 4 0101 2 0110 0 0111 2 1000 3 1001 4 1010 5 1011 6 1100 7 1101 8 1110 9 1111 10 ...

Page 51: ...011 16 dB 0100 14 dB 0101 12 dB 0110 10 dB 0111 8 dB 1000 7 dB 1001 6 dB 1010 5 dB 1011 4 dB 1100 3 dB 1101 2 dB 1110 1 dB 1111 0 dB Table 76 LnAT bits dynamic range compression LnAT 3 0 Dynamic range compression DRC dB relative to volume 0000 31 0001 29 0010 27 0011 25 0100 23 0101 21 0110 19 0111 17 1000 16 1001 15 1010 14 1011 13 1100 12 1101 10 ...

Page 52: ...compression DRC db relative to volume LnAT 0000 0001 38 dB 0010 36 dB 0011 33 dB 0100 31 dB 0101 30 dB 0110 28 dB 0111 26 dB 1000 24 dB 1001 22 dB 1010 20 dB 1011 18 dB 1100 15 dB 1101 12 dB 1110 9 dB 1111 6 dB Table 76 LnAT bits dynamic range compression continued LnAT 3 0 Dynamic range compression DRC dB relative to volume ...

Page 53: ... channels using the same power device There are 8 possible settings the appropriate setting varying based on the application and connections to the DDX power devices D7 D6 D5 D4 D3 D2 D1 D0 Reserved C2OT2 C2OT1 C2OT0 Reserved C1OT2 C1OT1 C1OT0 0 1 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved C4OT2 C4OT1 C4OT0 Reserved C3OT2 C3OT1 C3OT0 0 1 1 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved C6OT2 C6OT1 C...

Page 54: ...eives is dependent upon that channels CnOM register bits D7 D6 D5 D4 D3 D2 D1 D0 Reserved C2OM2 C2OM1 C2OM0 Reserved C1OM2 C1OM1 C1OM0 0 0 0 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved C4OM2 C4OM1 C4OM0 Reserved C3OM2 C3OM1 C3OM0 0 0 1 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved C6OM2 C6OM1 C6OM0 Reserved C5OM2 C5OM1 C5OM0 0 1 0 1 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved C8OM2 C8M1 C8OM0 Reserved C7...

Page 55: ...15 8 0x41 D7 D6 D5 D4 D3 D2 D1 D0 Reserved CFA9 CFA8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0 0 0 0 0 0 0 0...

Page 56: ... D3 D2 D1 D0 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16 0 0 0...

Page 57: ...llection of I2 C registers are dedicated to this function One contains a coefficient base address five sets of three store the values of the 24 bit coefficients to be written or that were read and one contains bits used to control the write of the coefficient s to RAM The following are instructions for reading and writing coefficients D7 D6 D5 D4 D3 D2 D1 D0 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B...

Page 58: ...C address 0x41 8 read bottom 8 bits of coefficient b2 in I2 C address 0x42 9 read top 8 bits of coefficient a1 in I2 C address 0x43 10 read middle 8 bits of coefficient a1 in I2 C address 0x44 11 read bottom 8 bits of coefficient a1 in I2 C address 0x45 12 read top 8 bits of coefficient a2 in I2 C address 0x46 13 read middle 8 bits of coefficient a2 in I2 C address 0x47 14 read bottom 8 bits of co...

Page 59: ...efficient a1 in I2C address 0x45 12 write top 8 bits of coefficient a2 in I2C address 0x46 13 write middle 8 bits of coefficient a2 in I2C address 0x47 14 write bottom 8 bits of coefficient a2 in I2C address 0x48 15 write top 8 bits of coefficient b0 in I2C address 0x49 16 write middle 8 bits of coefficient b0 in I2C address 0x4A 17 write bottom 8 bits of coefficient b0 in I2C address 0x4B 18 writ...

Page 60: ...s postscale factor can be used in conjunction with an ADC equipped micro controller to perform power supply error correction All channels can use the channel 1 by setting the postscale link bit Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 CxMIX1 CxMIX2 CxMIX3 CxMIX4 CxMIX5 CxMIX6 CxMIX7 CxMIX8 Channel x Table 80 RAM block for biquads mixing and bass management In...

Page 61: ... Channel 2 Postscale C2PstS 0x7FFFFF 415 0x19F Channel 8 Postscale C8PstS 0x7FFFFF 416 0x1A0 Channel 1 Mix 1 1 C1MX11 0x7FFFFF 417 0x1A1 Channel 1 Mix 1 2 C1MX12 0x000000 423 0x1A7 Channel 1 Mix 1 8 C1MX18 0x000000 424 0x1A8 Channel 2 Mix 1 1 C2MX11 0x000000 425 0x1A9 Channel 2 Mix 1 2 C2MX12 0x7FFFFF 479 0x1DF Channel 8 Mix 1 8 C8MX18 0x7FFFFF 480 0x1E0 Channel 1 Mix 2 1 C1MX21 0x7FFFFF 481 0x1E1...

Page 62: ...2 0x4F 0x50 DCC bits determine the 16 MSBs of the distortion compensation coefficient This coefficient is used in place of the default coefficient when DCCV 1 D7 D6 D5 D4 D3 D2 D1 D0 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0 0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 1 1 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10...

Page 63: ...quivalent to negative maximum ripple peak as a percentage of Vcc MPR scaled by the inverse of maximum ripple p p as percentage of full scale analog input to ADC Represented as a 1 11 signed fractional number 8 4 2 PSC3 correction normalization value CNV 0x53 Equivalent to 1 1 MPR expressed as a 0 12 unsigned fractional number D7 D6 D5 D4 D3 D2 D1 D0 RCV11 RCV10 RCV9 RCV8 RCV7 RCV6 RCV5 RCV4 0 0 0 ...

Page 64: ...5 0 057 B 0 17 0 22 0 27 0 0066 0 0086 0 0106 C 0 09 0 0035 D 11 80 12 00 12 20 0 464 0 472 0 480 D1 9 80 10 00 10 20 0 386 0 394 0 401 D3 7 50 0 295 e 0 50 0 0197 E 11 80 12 00 12 20 0 464 0 472 0 480 E1 9 80 10 00 10 20 0 386 0 394 0 401 E3 7 50 0 295 L 0 45 0 60 0 75 0 0177 0 0236 0 0295 L1 1 00 0 0393 K 0 min 3 5 min 7 max ccc 0 080 0 0031 TQFP64 10 x 10 x 1 4mm 0051434 E ccc Dimension mm Inch...

Page 65: ... 4 65 67 10 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc Automode is a trademark of Apogee Technology Inc Dolby is a registered trademark of Dolby Laboratories ECOPACK is a registered trademark of STMicroelectronics ...

Page 66: ... value for bit AMPS in register AUTO3 on page 41 Corrected bit names in Coefficient a1 data register bits 23 16 0x43 on page 56 Updated RAM block index values which are greater than index 425 in Table 80 on page 60 Added Dolby in Chapter 10 Trademarks and other acknowledgements on page 65 18 Sep 2009 3 Updated description of bitfield AMGC in register AUTO1 on page 39 Updated description of bit AMP...

Page 67: ...WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICAT...

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