Power reduction modes
UM0404
DocID13284 Rev 2
). The discharging of the external capacitor provides a delay that allows the
oscillator and PLL circuits to stabilize before the internal CPU and Peripheral clocks are
enabled. When the voltage on RPD pin drops below the threshold voltage (about 2.5 V), the
Schmitt Trigger clears Q2 flip-flop, thus enabling the CPU and Peripheral clocks, and the
device resumes code execution.
If the Interrupt was enabled (bit CCxIE = ‘1’ in the respective CCxIC register) before
entering Power Down mode, the device executes the interrupt service routine, and then
resumes execution after the PWRDN instruction (see note below). If the interrupt was
disabled, the device executes the instruction following PWRDN instruction, and the Interrupt
Request Flag (bit CCxIR in the respective CCxIC register) remains set until it is cleared by
software.
Note:
Due to internal pipeline, the instruction that follows the PWRDN instruction is executed
before the CPU performs a call of the interrupt service routine when exiting Power Down
mode.
Figure 212. Simplified power down exit circuitry
Exiting from Interruptible Power Down is also possible through the CAN Receive lines and
I
2
C Serial Clock line: if properly enabled (through CC8IC and CC9IC registers), an activity
on pins P4.5 and P4.4 is interpreted as a fast external interrupt event able to wake-up the
device. For more details refers also to
Section 5.6.1: Fast external interrupts on page 115
Enter
External
Interrupt
Reset
stop PLL
stop oscillator
V
DD
D
Q
Q
cd
system clock
CPU and Peripherals Clocks
RPD
V
DD
exit_pwrd
en_clk_n
Pull-Up
Weak Pull-Down
(~ 200
μ
A)
Power Down
Q2
V
DD
D
Q
Q
cd
Q1