Figure 6.
JTAG, JTAG/LFAST LVDS interface, SIPI I/F and SMPS interface CONN
J37
STRIP
2
1
3
4
5
6
J36
STRIP
2
1
3
4
5
6
SIPI interface
JTAG interface
GND
SIPI_TXP
PF14
SIPI_TXN
GND
SIPI_RXP
SIPI_RXN
VDD_HV_IO_JTAG
EVTI
TDO
GND
TDO
TDI
TCK
TCK
(pg3)
TMS
EVTI
(pg3)
JCOMP
TDI
GND
(VSS)
JTAG Connector
Place CAPS as close to
connector pins as
possible but do NOT fit
caps at board assembly.
JCOMP
(VSS)
TMS
(VSS)
(VSS)
SIPI_TXP
(pg3)
SIPI_RXP
(pg3)
SIPI_RXN
(pg3)
SIPI_TXN
(pg3)
TMS
VDD_HV_IO_JTAG
JCOMP
VDD_HV_IO_JTAG
VDD_HV_IO_JTAG
DRCLK
PORST
J20
ERF8-005-05.0-L-DV-L-TR
1
2
3
4
5
6
7
8
9
10
11
12
EVTI_0/EVTO_0
TDI, TDO, TCK, TMS & JCOMP are not connected to
daughter card.
PORST, ESR0, EVTI and EVTO are connected to daughtercard
ESR0 (pg3,5)
PORST (pg3,5)
TDO
TDI
TMS
JCOMP
J18
N2514-6002RB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
10 Pin Version
JTAG/LFAST LVDS INTERFACE
R25
DNM
VDD_HV_IO_JTAG
R20
DNM
R3
DNM
DNP
R4
10K
C56
DNM
C57
DNM
J41
STRIP3PMD-2MM
1
2
3
J42
STRIP3PMD-2MM
1
2
3
R23
DNM
R17
DNM
GND
GND
C132
DNM
0603
C133
DNM
0603
PF14 (pg3,6)
GND
GND
EVTO
EVTO
(pg3)
C134
27pF
0603
R28
DNM
PORST_ESR0
CN1
SAMTEC TFM-105-02-L-D-WT
1
2
3
4
5
6
7
8
9
10
11 12
GND
R24
DNM
DNP
R19
0R
R18
0R
R22
0R
R21
0R
PORST
(pg3,5)
PORST_ESR0
SMPS_REGULATOR_OUT
PG15
PIN 141
(smps_nmos1)
PIN 140
(smps_vlx)
PIN 138
(smps_pmos0)
PH0
PH1
GND
VDD_HV_IO_MAIN
Previson SPC58EE84E7/SPC58NE84E7 DC-DC Regulator
PH[0..15]
(pg3,6)
PG[0..15]
(pg3,6)
TDO_RxDATA_P
(pg3)
TDI_TxDATA_N
(pg3)
TMS_TxDATA_P
(pg3)
JCOMP_RxDATA_N
(pg3)
EVTI
(pg3)
EVTO
(pg3)
ESR0
(pg3,5)
TCK
(pg3)
UM2723
-
Rev 1
page
21
/28
UM2723
Schematic