Figure 13.
Debug connectors
LFAST interface
DRCLK
JTAG interface
Place CAPS as close to
con
nector pins as
possible but do NOT fit
caps at board assembly.
JTAG Connector
(VSS)
(VSS)
(VSS)
(VSS)
TDI, TDO, TCK, TMS & JCOMP are not connected to
daughter card.
PORST, ESR0, EVTI and EVTO are connected to daughtercard
FCC
U_ERROR0
FCCU_ERROR1
METTERE LE 2 LABEL COME
SERIGRAFIA SU PCB
SIPI interface
CLK
SERIGRAFIA
PA14 / RDY / SIPI_TXN
CONFIGURATION JUMPERS
TESTMODE
STRIP 2.54 12x2 CONNECTOR
FCCU TEST CONNECTOR
47uF
47uF
100R
100R
10 K
10 K
JCOMP_RxDATA_N/PA[5]
TMS_TxDATA_P/PA[7]
TCK/PA[6]
TDO
P ORS T
P A6-TCK
TMS
TDI
J COMP
TMS
J COMP
EVTO
P ORS T
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J COMP
TMS
TDI
TDO
P A6-TCK
P ORS T
P ORS T
TMS
EVTO
J COMP
P A6-TCK
P A5-J COMP
TDO_LF
P A7-TMS
TDI_LF
P ORS T
P J 3
P A14
P A8
P A9
P J 3-EVTO
P A14-RDY-S IP I_TXN
P A9-TDO
P A8-TDI
RDY
P B11
P C2
EVTO/ES R0
EVTO/ES R0
P D6-S IP I_TXP
RDY
P M14-CLK
P F13-S IP I_RXN
P D7-S IP I_RXP
EVTO
EVTO
TES TMODE
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
P D12
P E2
P D13
P E1
P B0
P C9
P A2
P A1
3.3V_S R
P F13
P D6
P D7
P M14
ES R0
P C1-ES R0
P C1
P Q4
P E12
P D1
P B2
P A12
P D4
P B10
P E7
P C8
TDO
TDI
TDO_LF
TDI_LF
R90
0R
C74
DNM
FCCU1
S TRIP 2P MD-2MM-O
1
2
CN4
S AMTEC TFM-105-02-L-D-WT
1
2
3
4
5
6
7
8
9
10
1
2
1
1
J 11
S TRIP 3P MD-2MM
1
2
3
R26 DNM
C76 DNM
R33
0R
U4
S TRIP 2x36P MD
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
CN2
ERF8-005-05.0-L-DV-L-TR
1
2
3
4
5
6
7
8
9
10
11
12
R91
0R
C78
27pF
50V
J 13
S TRIP 3P MD-2MM
1
2
3
R22
DNM
R27 DNM
C77 DNM
TP 3
R32
0R
J 10
S TRIP 3P MD-2MM
1
2
3
TP 5
R21
DNM
R34
DNM
TP 4
R29
DNM
J 14
S TRIP 3P MD-2MM
1
2
3
J 12
S TRIP 3P MD-2MM
1
2
3
J 16
S TRIP 2P MD-2MM
1
2
R24
DNM
R31 DNM
R30
10K
R25
DNM
C75
DNM
J 15
S TRIP 3P MD-2MM
1
2
3
R35
DNM
R28
10K
R23
DNM
CN3
N2514-6002RB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
UM2731
-
Rev 1
page 28/37
UM2731
Schematic
