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Revision history

STCF03

34/35

  

12 Revision 

history

         

Table 17.

Document revision history 

Date

Revision

Changes

30-Jan-2007

1

First Release.

27-Mar-2007

2

The OVP min. value on table 5 is changed: 5.5 V ==> 5.3 V.

28-Aug-2007

3

Modified 

Table 5

.

12-Sep-2007

4

Modified 

Figure 2

.

10-Sep-2008

5

Added 

Figure 4 on page 14

.

Summary of Contents for QFN20

Page 1: ...ed and shorted LED failure detection and protection Chip over temperature detection and protection 1 A shutdown current Packages QFN20 4x4 TFBGA25 3x3 Applications Cell phone and smart phone Camera fl...

Page 2: ...7 2 3 ATN pin 13 7 2 4 ADD pin 14 7 2 5 TMSK pin 14 7 3 I C bus interface 15 7 4 Data validity 15 7 5 Start and stop conditions 15 7 6 Byte format 16 7 7 Acknowledge 16 7 8 Writing to a single regist...

Page 3: ...24 9 Detailed description 25 9 1 PowerON reset 25 9 2 Shutdown shutdown with NTC 25 9 3 Ready mode 25 9 4 Single or multiple Flash using external P temporization 25 9 5 External P temporization using...

Page 4: ...cal characteristics 11 Table 7 Address table 14 Table 8 Interface protocol 17 Table 9 I C register mapping function 20 Table 10 Command register 20 Table 11 Dimming register 21 Table 12 Auxiliary regi...

Page 5: ...tiple register with incremental addressing 18 Figure 11 Reading from a single register 19 Figure 12 Reading from multiple registers 19 Figure 13 Flash and Torch current vs dimming value 21 Figure 14 V...

Page 6: ...programmable time out function protects the LED in case of a wrong command from the P An optional external NTC resistor is supported to protect the LED against over heating In mobile phone applicatio...

Page 7: ...Diagram STCF03 7 35 2 Diagram Figure 1 Block diagram...

Page 8: ...A5 FB2 RTR bypass 7 B4 FB2S Feedback sensing pin ILED RFL 8 E2 GND Signal ground 9 D4 ADD I C address selection 10 D5 AUXL Auxiliary LED output 11 C5 TMSK TX mask input 12 B1 C1 PVBAT Power supply vol...

Page 9: ...iliary LED 0 3 to VI 0 3 V FB1 FB2 FB2S Feedback and sense voltage 0 3 to 3 V SCL SDA TRIG ATN ADD TMSK Logic Pin 0 3 to VI 0 3 V RX Connection for reference resistor 0 3 to 3 V NTC Connection for LED...

Page 10: ...Operation of the STCF03 is not limited to the choice of these external components Figure 3 Application schematic Table 5 List of external components Component Manufacturer Part number Value Size CI TD...

Page 11: ...3 V to 5 5 V 0 20 VO Regulated voltage range 2 5 5 3 V FB1 Feedback voltage Torch mode 30 250 mV FB2 Feedback voltage Flash mode 30 250 mV IO Output current tolerance Flash mode IO 160 mV RFL 10 10 RO...

Page 12: ...0 2 V IOZ Output logic leakage current ATN VOZ 3 3 V 1 mA VIL Input logic signal level SCL SDA TRIG TEST ADD VI 2 7 V to 5 5 V 0 0 4 V VIH 1 4 3 TON LED current rise time ILED 0 to ILED max 2 ms Table...

Page 13: ...ses can occur Boost region VO VBAT this configuration is used in most of the cases as the output voltage VO VfLED ILED x RFL is higher than VBAT Buck region VO VBAT Buck Boost region VO VBAT 7 2 Logic...

Page 14: ...implement the TX masking function This function has effect only for flash current settings higher than 200 mA bit FDIM_3 1 Under this condition when this pin is pulled high by the P the current flowin...

Page 15: ...he data on the SDA line must be stable during the high period of the clock The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW 7 5 Start and stop condi...

Page 16: ...during the acknowledge clock pulse see Figure 8 The peripheral STCF03 that acknowledges has to pull down LOW the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during t...

Page 17: ...face protocol is composed A start condition START A Device address R W bit read 1 write 0 A Register address byte A sequence of data n 1 byte acknowledge A stop condition STOP Table 8 Interface protoc...

Page 18: ...se of STCF03 again Then the master generates a START bit again and sends the device address followed by the R W bit which is 1 now STCF03 confirms the receiving of the address R W bit by an acknowledg...

Page 19: ...T A C K R W R E A D DEVICE ADDRESS 7 bits DATA L S B S T O P N O A C K SDA LINE S T A R T DEVICE ADDRESS 7 bits A C K W R I T E M S B L S B R W ADDRESS OF REGISTER A C K M S B L S B S T A R T A C K R...

Page 20: ...ust be set in advance Both triggering modes can benefit of the internal flash time counter that uses the TRIG_EN bit and can work either as a safety shut down timer or as a flash duration timer Flash...

Page 21: ...ped by resetting TRIG_EN bit and simultaneously the ATN pin is set to true LOW to alert the P that the maximum time has been reached FTIM value remains unaltered at the end of the count 8 6 TDIM_0 3 T...

Page 22: ...XI register Note LED current values refer to RFL 0 27 RTR 1 8 Table 12 Auxiliary register AUX_REG write mode MSB LSB SUB ADD 02 AUXI_3 AUXI_2 AUXI_1 AUXI_0 AUXT_3 AUXT_2 AUXT_1 AUXT_0 Power ON SHUTDOW...

Page 23: ...ld corresponds to a warning temperature value at the LED measured by the NTC The device is still operating but a warning is sent to the P This bit is reset by the STCF03 following a read operation of...

Page 24: ...d is never reached the bit stays HIGH ATN pin is pulled down and the device will not start This bit is reset following a read operation of the STAT_REG Figure 14 VOUTOK_N behavior Table 16 Status regi...

Page 25: ...ister settings are allowed to be executed immediately Only in this mode the auxiliary LED is operational and can be turned ON and set at the desired brightness using the AUX REGISTER The device enters...

Page 26: ...it is necessary to set the TRIG_EN bit in advance For soft triggering the TRIG pin has to be kept High logic level or wired to VBAT and the flash can be started by setting the FTIM and the TRIG_EN thr...

Page 27: ...55mA 0 50 100 150 200 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 step mA VI 2 7V VI 3 6V VI 5 5V 0 50 100 150 200 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 step mA VI 2 7V VI 3 6V VI 5 5V 0 100...

Page 28: ...VI 5 5 V ready mode Figure 22 Start up in flash mode 800 mA at VI 3 6 V Figure 23 Line transient in flash mode 800 mA change of VI from 2 7 V to 3 3 V in 10 s 0 0 5 1 1 5 2 2 5 3 40 C 25 C 85 C Temp...

Page 29: ...packages have a lead free second level interconnect The category of second level interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum...

Page 30: ...1 6 157 5 163 4 D1 3 75 147 6 D2 A 1 55 1 70 1 85 61 0 66 9 72 8 D2 B 1 95 2 10 2 25 76 8 82 7 88 6 D2 C 2 15 2 30 2 45 84 6 90 6 96 5 E 3 85 4 00 4 15 151 6 157 5 163 4 E1 3 75 147 6 E2 A 1 55 1 70 1...

Page 31: ...p Max Min Typ Max A 1 0 1 1 1 16 39 4 43 3 45 7 A1 0 25 9 8 A2 0 78 0 86 30 7 33 9 b 0 25 0 30 0 35 9 8 11 8 13 8 D 2 9 3 0 3 1 114 2 118 1 122 0 D1 2 78 8 E 2 9 3 0 3 1 114 2 118 1 122 0 E1 2 78 8 e...

Page 32: ...32 35 Dim mm inch Min Typ Max Min Typ Max A 330 12 992 C 12 8 13 2 0 504 0 519 D 20 2 0 795 N 99 101 3 898 3 976 T 14 4 0 567 Ao 4 35 0 171 Bo 4 35 0 171 Ko 1 1 0 043 Po 4 0 157 P 8 0 315 Tape reel Q...

Page 33: ...35 Dim mm inch Min Typ Max Min Typ Max A 330 12 992 C 12 8 13 2 0 504 0 519 D 20 2 0 795 N 60 2 362 T 14 4 0 567 Ao 3 3 0 130 Bo 3 3 0 130 Ko 1 60 0 063 Po 3 9 4 1 0 153 0 161 P 7 9 8 1 0 311 0 319 T...

Page 34: ...ble 17 Document revision history Date Revision Changes 30 Jan 2007 1 First Release 27 Mar 2007 2 The OVP min value on table 5 is changed 5 5 V 5 3 V 28 Aug 2007 3 Modified Table 5 12 Sep 2007 4 Modifi...

Page 35: ...NTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS E...

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