ST EVALSP1310CPU, User Manual, Page: 16 / 36

Block descriptions UM1585
16/36 Doc ID 023872 Rev 1
Note: When DIP switch SWx-x is in the ON position, the bit value is 0. When the DIP switch is in
the OFF position, the bit value is 1.
SPEAr GMII I/F VDD could be 3.3 V or 2.5 V. It is possible test this functionality by moving
two jumpers: one for SPEAr pads and one for the external DP83865 (U5).
The two jumpers must also be aligned with strapping option SW4.2.
Figure 10. SPEAr GMII I/F voltage selector
Figure 11. Gigabit PHY Ethernet voltage selector
Three JP are used as DP83865 (U5) strapping option: JP17, JP18 and JP19.
Table 6. Jumper configurations
Default Settings
Description
On Off
JP6 JP11
Phy address bit 0
1 2 3 1 2 3
JP7 JP12
Auto negotiation enable bit
1 2 3 1 2 3
JP8 JP13
Full duplex select bit
1 2 3 1 2 3
JP9 JP14
Speed select bit 1 (see Table 3: J1 NAND expansion
connector pin assignment and Table 4: PCIe clock
settings (default settings) )
1 2 3 1 2 3
JP10 JP15
Speed select bit 1 (see Table 3: J1 NAND expansion
connector pin assignment and Table 4: PCIe clock
settings (default settings) )
1 2 3 1 2 3
JP16
1 2
3
3.3 V
JP16
1 2
3
2.5 V
JP42
1 2 3
3.3 V
JP42
1 2
3
2.5 V