UM1585
Block descriptions
Doc ID 023872 Rev 1
The output frequency must be set at 100 MHz. On the EVALSP1310CPU board, the default
settings is S2 ... S0 = 0.
4.5 Ethernet
subsystem
This subsystem is based on the Ethernet GMII PHY DP83865 (U5) and a connector that
also includes all the required magnetics. Several configuration jumpers are present and also
several LEDs to display the line status/activity.
4.5.1
Configuration jumpers and switches
Table 4.
PCIe clock settings (default settings)
S2 (SW2-3)
S1(SW2-2)
S0 (SW2-1)
Spread %
Spread type
Output frequency
0
0
0
-0.5
Down
100
0
0
1
-1.0
Down
100
0
1
0
-1.5
Down
100
0
1
1
No spread
Not applicable
100
1
0
0
-0.5
Down
200
1
0
1
-1.0
Down
200
1
1
0
-1.5
Down
200
1
1
1
No spread
Not applicable
200
Table 5.
Switch 1 configuration
Pin
Description (default settings)
1
Phy address bit 1 (0 - ON)
2
Phy address bit 2 (1 - OFF)
3
Phy address bit 3 (0 - ON)
4
Phy address bit 4 (0 - ON)
5
MULTIPLE NODE ENABLE
: This pin determines if the PHY advertises Master (multiple
nodes) or Slave (single node) priority during 1000BASE-T Auto-Negotiation.
1: multiple node priority (switch or hub)
0: single node priority (NIC) (0 - ON)
6
AUTO MDIX ENABLE
: This pin controls the automatic pair swap (Auto-MDIX) of the
MDI/MDIX interface.
1: pair swap mode enabled
0: Auto-MDIX disabled, and part defaulted into the mode preset by the
MAN_MDIX_STRAP pin. (0 - ON)
7
CLOCK TO MAC ENABLE
:
1: CLK_TO_MAC clock output enabled
0: CLK_TO_MAC disabled (1 - OFF)
8
Not used