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PulseBlasterESR  QuadCore 250 (Turbo)

 II. Installing and Using Your PulseBlasterESR QuadCore Board

Installation

     To install the board you must complete the following three steps:

   

 

-  Install the latest SpinAPI version, available at the address 

http://spincore.com/support/spinapi/

     - Shut down computer, insert PulseBlasterESR QuadCore Turbo 250 card, and fasten the PC bracket 
securely with a screw.
     - Power up and follow the installation prompts.

Now you are ready to run the test programs provided in the SpinAPI package.  

Note: When installing the hardware, the device may show up as PulseBlasterESR-Pro, this is OK.
Note: The PulseBlaster Interpreter that is included in the SpinAPI package CANNOT be used to program the 
PBESR QuadCore board.
Note: To compile and run your own C programs, you may want to download the 

SpinAPI Tools

 package that 

contains a pre-configured compiler; the 

SpinAPI Tools

 package is also available for download at the URL above.

General API Programming Information

Four test programs (executables and their C source files) are available for testing the boards.   Assuming the 

default installation, the test programs will be available on the computer at the following location:  Windows 
“Start” 

 All Programs 

 SpinAPI 

 PBESR_QuadCore (the default installation location is: C:\Program 

Files\SpinCore\SpinAPI\PBESR-QuadCore).  The .c files can be modified and recompiled to create custom test 
programs. 

Each core can be programmed with a unique pulse program by using the pb_select_core(unsigned int 

core_sel) function, where the lower four bits of core_sel are used to select the cores (bit0 corresponds to Core0, 
bit1 corresponds to Core1, etc) and multiple combinations are acceptable (i.e. a value of 0xF, or 15 will select all 
four cores).

The overall system timing is based on Core0 in order to ensure that all cores are precisely synchronized. This 

requires that Core0 be the 

last

 core (or part of the group of last cores) that is programmed before starting 

execution of the pulse program(s).

Two separate SpinAPI functions are used to write pulse programs for the PulseBlasterESR QuadCore: 

pb_4C_inst(int flag, double length) and pb_4C_stop(void).

pb_4C_inst(...) is used to define the pulse program.  The input parameter 'flag' must either be '1' to turn the 

flag on, or '0' to turn the flag off.  The input parameter 'length' defines the time interval for the current instruction 
and must be multiplied by 'ns' (nanoseconds), 'us' (microseconds), or 'ms' (milliseconds).

pb_4C_stop() defines the end of the pulse program.  

It is 

very important to note

 that because the synchronization is based on Core0, if Core0's pulse program is 

still running, the other cores may continue to output values from memory even after the pb_4C_stop() instruction. 
Also, if Core0's pulse program stops, it will cause all other cores to stop even if they have not completed their 
pulse program.  For this reason it is highly recommended that the pulse program for Core0 has the longest 
duration, and the pulse programs for the other cores are extended using the pb_4C_inst(...) instruction with a '0' 
output so that the total duration of each pulse program is the same causing them to stop at exactly the same 
time.

www.spincore.com

5

02/17/09

Summary of Contents for PulseBlasterESR QuadCore 250 Turbo

Page 1: ...PulseBlasterESR QuadCore 250 Turbo Owner s Manual SpinCore Technologies Inc http www spincore com ...

Page 2: ... Technologies Inc reserves the right to make changes to the product s or information herein without notice PulseBlaster QuadCore PulseBlaster SpinCore and the SpinCore Technologies Inc logos are trademarks of SpinCore Technologies Inc All other trademarks are the property of their respective owners SpinCore Technologies Inc makes every effort to verify the correct operation of the equipment This e...

Page 3: ...ct Overview 4 Programming Paradigm 4 II Installing and Using Your PulseBlasterESR QuadCore Board 5 Installation 5 General API Programming Information 5 III Test Programs 6 IV Available Options 7 V Contact Information 7 VI Document Information Page 8 www spincore com 3 02 17 09 ...

Page 4: ...terval length is 229 clock cycles 2 15 seconds Each core has 1k 1024 memory words available for writing pulse programs i e there can be up to 1024 lines in your pulse program per core The basic architecture of the individual PulseBlaster processor cores is described in multiple documents including the Manuals for PulseBlaster and PulseBlasterESR boards available on line at the SpinCore s website w...

Page 5: ...gned int core_sel function where the lower four bits of core_sel are used to select the cores bit0 corresponds to Core0 bit1 corresponds to Core1 etc and multiple combinations are acceptable i e a value of 0xF or 15 will select all four cores The overall system timing is based on Core0 in order to ensure that all cores are precisely synchronized This requires that Core0 be the last core or part of...

Page 6: ...tput should be one 20 ns pulse on each BNC output connector and all four pulses should appear simultaneously on all four channels NOTE When attaching an oscilloscope to the board to observe the pulses care should be taken to use cables of the same type and length for each channel as skew can be induced due to propagation delays Conversely any inherent variations in on chip propagation delays can b...

Page 7: ...itional TTL output bits per core custom design Please contact SpinCore Technologies Inc for more information questions or suggestions We look forward to hearing from you and helping you in your projects Please find our contact information below V Contact Information SpinCore Technologies Inc 4623 NW 53rd Avenue Suite 5 Gainesville Florida 32653 USA Phone 1 352 271 7383 Fax 1 352 371 8679 Website h...

Page 8: ...Number DA 2 File Name PBESR_QuadCore_Manual Document Location S Product_Folders Manuals PBESR_QuadCore Original Document Created Chris Hett 2009 01 22 Revision History Chris Hett 2009 02 03 Edited Figure 1 to more correctly display board architecture with timing based on Core0 Updated formatting www spincore com 8 02 17 09 ...

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