PulseBlasterESR-PRO
Board Architecture
Block Diagram
Figure 1 presents the general architecture of the PulseBlasterESR-PRO system. The major building
blocks are the SRAM memory, the PulseBlaster core, the integrated bus controller (IBC), the counter, and
the output buffers. The entire logic design, including the SRAM memory and output buffers, is contained
on a single silicon chip, making it a System-on-a-Chip design. User control to the system is provided
through the IBC over the PCI bus.
Output Signals
The PulseBlasterESR-PRO allows for 21 digital output signal lines. On the PCI boards, all 21 signal
lines are routed to two sets of 26-pin IDC on-board connectors. The first four output bits are also routed
to four bracket mounted BNC connectors. On the USB system, all 21 signal lines are routed to 21 BNC
connectors. The output signals are impedance matched to 50 ohm.
The 21 individually controlled digital output bits comply with the 3.3V TTL-levels’ standard, and are
capable of delivering
25 mA per bit/channel. Keep in mind that this is sufficient to provide a signal to a
132 ohm load, but if more current is necessary beyond this, the individual bits/channels can be driven in
parallel.
2019/09/26
Figure 1:
PulseBlasterESR-PRO Board Architecture. The clock oscillator signal is derived
from an on-chip PLL circuit typically using a 50 MHz on-board reference clock.
