Sperry Rand UNIVAC 1219B Technical Manual Download Page 78

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Summary of Contents for UNIVAC 1219B

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Page 2: ...L MANUAL for TYPE 12191 DIGITAL DATA COMPUTER VOLUME 1 SECTIONS 1 8 PX 4682 1 2 AUGUST 1968 July 1972 Change 3 UNIVAC DEFENSE SYSTEMS DIVISION St Paul Minnesota 1968 1969 1970 1972 by SPERRY RAND CORP...

Page 3: ...35 4 36 4 37 to 4 79 4 80 4 81 to 4 84 4 85 4 86 to 4 96 4 97 4 98 4 99 to 4 149 4 150 5 1 to 5 6 6 1 to 6 16 CHANGE IN EFFECT Original Change 1 Change 2 Change 3 Change 3 Change 2 Change 1 Original C...

Page 4: ...137 Supplement Change 3 9 167 Supplement Change 3 9 54 Change 3 9 137 and 9 138 Change 1 9 167 and 9 168 Change 1 9 55 and 9 56 Change 1 9 138 Supplement Change 3 9 168 Supplement Change 3 9 57 Change...

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Page 6: ...LIST OF SECTIONS SECTION VOLUME l GENERAL DESCRIPTION 1 2 INSTALLATION 1 3 OPERATOR S SECTION 1 4 THEORY OF OPERATION 1 5 TROUBLESHOOTING 1 6 SERVICE AND REPAIR 1 7 PARTS LIST 1 8 SYMBOLOGY 1 9 FUNCTI...

Page 7: ...l Time Clock g Interrupts h Control Section 1 Console Control 2 Timing Circuits 3 Program Translation and Control 4 Registers 5 Special Circuits i I O Section 1 Class of Operation 2 I O Communication...

Page 8: ...uirements f Installation Requirements Cabling Instructions a Power Cable b I O Signal Cables Computer Ground Requirements Preoperational Inspection and Preliminary Testing a Visual Inspection b Initia...

Page 9: ...2 I O Operations 3 I O Timing c Arithmetic Section 1 General 2 Functional Description 3 Operation d Memory Section Cl General 2 Main Memory 3 Control Memory 4 Bootstrap Memory Power Supplies and Powe...

Page 10: ...g a Drawer c Opening a Chassis d Removing a Drawer e Fuse Replacement f Temperature Sensing Switch Location g Voltage Protection Network Location h Extending the Power Supply i Removing the Power Supp...

Page 11: ...ymbology a Inverter b AND Inverters c AND OR Inverters d OR Inverter e Flip Flops f Amplifier Driver g Input Amplifiers h Output Amplifiers and Line Drivers i Indicator Driver Reference Designators a...

Page 12: ...Computer Drawers and Chassis Printed Circuit Module Type A Printed Circui t Module Type B SECTION 2 INSTALLATION Computer Clearance Requirements Location and Access to Cable Entry Panel Location of C...

Page 13: ...Transfer Typical Stage of Arithmetic Selector Simplified Diagram Single Stage of Half Subtractor Single Stage of Borrow Generator Add Instruction Subtract Instruction Multiply Sequence Divide Sequenc...

Page 14: ...nded Fil ter Location Memory Stack Location Memory Waveforms Clock Pulse Timing Phase Generator Simplified Strobe Pulse Sense Readout Comparison SECTION 7 PARTS LIST Digital Data Computer front view D...

Page 15: ...002160 Inverter Card Type 7002220 Differential Amplifier Card Type 7002321 Control Line Amplifier Card Type 7002331 Data Line Amplifier Card Type 7002341 High Speed Selector Card Type 7002730 Marginal...

Page 16: ...le 7500280 Module 7500280 Schematic Diagram Module 7500340 Block Diagram Module 7500340 Schematic Diagram Logic Symbol of One Circuit on 7500400 Module Module 7500400 Schematic Diagram Logic Symbol of...

Page 17: ...inted Circuit Module Complement Fuse Complement Power Control Switches and Relays SECTION 2 INSTALLATION I O Signal Cable Connections Cable Connector Pin Assignments JI J16 J21 J36 Pin Assignments for...

Page 18: ...d Sequences of Each Instruction I Sequence Rl Sequence RIR2 Sequence WSequence IBI Sequence IB2 Sequence SECTION 5 TROUBLESHOOTING Preventive Maintenance Schedule Preventive Maintenance Check off Shee...

Page 19: ...I 0 o 0 H G l H Z t r 4 DRAWER UNIT 6 DRAWER UNIT Figure 1 1 UNIVAC Type 12198 Digital Data Computer TJ CO oI CD I G l rrl Z rrl 0 r o rrl C l C l 0 H 0 t 3 H...

Page 20: ...ns is included with a description of each operation performed by the coded instruction word 4 SECTION 4 THEORY OF OPERATION Section 4 contains a detailed description of the equipment operation with pa...

Page 21: ...nd functional characteristics are listed in tables 1 2 and 1 3 respectively General characteristics are listed in table 1 4 Computer logic is divided into four functionally definable sections control...

Page 22: ...GENERAL DESCRIPTION Figure 1 2 NOTE TEST BLOCKS 1NSTALLED ON FRONT OF MEMORY DRAWER ONLY ON SN 14 48 Figure 1 2 Computer With Maximum of Eight Input Output Channels CHANGE 2 1 3...

Page 23: ...Figure 1 3 NOTE GENERAL DESCRIPTION TEST BLOCKS INSTALLED ON FRONT OF MEMORY DRAWER ONLY ON SN 14 48 Figure 1 3 Computer With Maximum of 16 Input Output Channels 1 4 CHANGE 2...

Page 24: ...ng A remote control console figure 1 6 can be connected to jack A12J17 A front panel indicator shows whether the computer is in local control or remote con trol The indicators and alarm on the remote...

Page 25: ...figure 1 9 consists of five logically de finable areas console control timing program translation and control registers and special circuits 1 CONSOLE CONTROL The console control area contains the co...

Page 26: ...to this rule is TS2 used only during complement A and complement AL instructions In the term T34 the 3 represents the third clock cycle the 4 indicates that phase four is the last usable phase occurr...

Page 27: ...ootstrap available upon special request Main memory access time is a maximum of 750 nanoseconds Control and bootstrap memory access time is a maximum of 300 nanoseconds Main and bootstrap memory cycle...

Page 28: ...nches REQUIRED ENVIRONMENTAL CONDITIONS OPERATING TEMPERATURE RANGE OVERTEMPERATURE WARNING OVERTEMPERATURE SHUTDOWN HUMIDITY MAXIMUM RELATIVE HEAT DISSIPATION LOGIC POWER BLOWER POWER 32 F OoC to 122...

Page 29: ...PUTERS INPUT DATA GENERAL DESCRIPTION INPUT OUTPUT MEMORY SECTION OUTPUT SECTION DATA A i 4 4 ARITH OR INPUT DATA CONTROL CONTROL CONTROL SECTION INPUT DATA ARITH ARITHMETIC DATA SECTION CONTROL Figur...

Page 30: ...Enter AL Add AL Subtract AL Add A Subtract A Multiply AL Divide A Indirect return jump Enter B Direct jump Enter B with constant Store zero Store B Store AL Store AU See format II instructions Selecti...

Page 31: ...ive Jump AL negative Enter AL with constant Add constant to AL Store ICR B jump Store address Store SR Return jump Illegal code Format II Instructions Set Set Set Not used input active output active e...

Page 32: ...t Remove interrupt lockout Remove external interrupt lockout Remove external interrupt lockout Set interrupt lockout Set interrupt lockout Set external interrupt lockout Set external interrupt lockout...

Page 33: ...e operation The five areas of the circuitry are the F register function code translator format II translator sequencer and command enable circuit The F register is a seven bit flip flop register which...

Page 34: ...of control functions These are the index registers ICR register SR register P register two S registers and K register Each register has a specific logic function to perform during the manipulation of...

Page 35: ...ement contents of a memory address during input and output operations and to update currently active index register during either B skip or B jump instructions The compare circuitry is used to collate...

Page 36: ...be connected to the odd channel of the channel pair No external I O cables can be connected to even channel while in the dual channel mode Control on dual channel is maintained by odd channel control...

Page 37: ...ol words are con tents of addresses 20 2K TBCW and 20 2K 1 current buffer control word For channels 10 thru 17 new buffer control words for the odd numbered channel are contents of address 220 2 K IO...

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Page 39: ...4 I I 2 I 3 1 4 1121 3 1 4 Til n LOW TI2 8 T52 HIGH 1 TI3 I TI4 T21 I T22 1 en I I T23 Q I 0 Q T24 0 J LI I Q nl I J LI Z t T32 I I U C Z 1 T33 I Z t T34 T41 1 T42 1 T43 L T44 SHADING INDICATES THE U...

Page 40: ...ontents of interrupt entrance registers from memory Reads terminal address control word and stores it in appropriate control memory address Reads initial address control word and stores it in appropri...

Page 41: ...nal interrupt codes are control information sent to the computer from a peripheral unit The external interrupt code specifies an error or special con dition that exists in a peripheral unit 5 I O INST...

Page 42: ...cified by buffer control words During output operations output data or external function words are removed from memory location specified by buffer control words and sent to the peripheral unit TWo me...

Page 43: ...0 11 instruction 41 2k or 241 2 k lO for a 50 12 instruction or 21 2k or 221 2 k lO for a 50 13 instruction For ex ample assume that the instruction word at address N specifies a 50 11 instruction for...

Page 44: ...ncy condition has occurred An emergency condition includes transmission of data with a parity error magnetic tape breakage card punch feed error voltage faults and several others Each individual error...

Page 45: ...nel a channel remains active at completion of the buffer this is necessa y be cause 0 ther data transfers may still be in operation on that channel The moni tor interrupt stores the odd channel input...

Page 46: ...unt cycle before a resume is received resume fault is set Since the RTC may be at any point in the count cycle as transmission begins the time varies when resume must be received This time is from 1 1...

Page 47: ...ut and 50 36 and 50 37 set external interrupt lock out The set interrupt lockout instruction prevents any interrupt from being processed except an instruction fault interrupt Any interrupt received du...

Page 48: ...rity 4 event on channel 178 has a higher priority than a priority 2 or 3 event on channel 168 If one or more priority A events are detected the highest prior ity event is processed and scan restarted...

Page 49: ...el is gated into the computer through input amplifiers e ACKNOWLEDGE Acknowledge circuitry informs peripheral devices of the status of I O operations by sending three types of acknowledge signals inpu...

Page 50: ...SLATORS TRANSLATORS r lORY CONTROL i t i REAL TIME CLOCK l F _ 18 INPUT I SELECTORS 1 0 SECTION I P REGISTER L I SI REGISTER I ISo REGISTER I A W I STC SELECT I I I S i STER I RE I ER I I eTOR r I T I...

Page 51: ...ata from the adder It is also used for shifting AL register is the lower half of the A register and receives data from the adder It is also used for left and right shifting with the Wregister The only...

Page 52: ...lsed to write a one at all 18 bit positions of the selected address If a zero is to be stored at any bit position in this word an inhibit pulse must be generated for those positions e SENSE AMPLIFIERS...

Page 53: ...s and ESI external function terminate ESI EFT control words I O channels 0 thru 7 EFMI for channel 0 entrance address ESI EFT for channel 0 control word EFMI for channel 1 entrance address ESI EFT for...

Page 54: ...te ESI EFT control words I O channels 10 thru 17 EFMI for channel 10 entrance address ESI EFT for channel 10 control word EFMI for channel 11 entrance address ESI EFT for channel 17 control word Outpu...

Page 55: ...ored In MAIN MEMORY position the computer references main memory addresses 00500 through 00537 where the magnetic tape load routine may be stored The referenced main memory addresses are not the NDRO...

Page 56: ...nizing interrupt entrance register Scale factor shift count word register Continuous data mode COM and external function EF buffer control registers for I O channels 0 thru 7 CDM EF for channel 0 term...

Page 57: ...channel 10 terminal address OBC for channel 10 current address OBC for channel II terminal address OBC for channel 17 current address Input buffer control IBC registers for I O channels 10 thru 17 IBC...

Page 58: ...c and dc voltages used throughout the control unit cabinet Fan assemblies provide forced air cooling for cabinet drawers A power control panel is provided to allow complete control of the computer fro...

Page 59: ...GENERAL DESCRIPTION Figure 1 10 Figure 1 10 Logic Drawer Extended ORIGINAL 1 41...

Page 60: ...Figure 1 11 GENERAL DESCRIPTION Figure 1 11 Typical Logic Chassis 1 42 ORIGINAL...

Page 61: ...lists dc power supply ou tpu ts 5 MAIN MEMORY POWER SUPPLY An additional power supply is located on the main memory chassis and provides voltages required specifically for main memory operation The v...

Page 62: ...Figure 1 12 4K MEMORY STACK TYPICAL GENERAL DESCRIPTION Figure 1 12 Main Memory Stack Locations A3A2 1 44 CHANGE 2...

Page 63: ...GENERAL DESCRIPTION Figure 1 13 Figure 1 13 Typical Main Memory Stack ORIGINAL 1 45...

Page 64: ...Figure 1 14 CONTROL MEMORY 00 128 WORDS 01 256 WORDS GENERAL DESCRIPTION BOOTSTRAP MEMORY Figure 1 14 Bootstrap and Control Memory Drawer A4 Locations 1 46 CHANGE 2...

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Page 67: ...GENERAL DESCRIPTION Figure 1 17 Power Supply Chassis Figure 1 17 LATCH FASTENERS ORIGINAL 1 49...

Page 68: ...ific meaning when applied to computer operation and circuitry This glossary is intended to delineate these terms and their specific meanings as they are written in this manual ABORT A condition within...

Page 69: ...irst group of instructions of a routine into storage then using these instructions to load the remainder of the routine BOOTSTRAP MEMORY A permanently wired nondestructive readout memory containing th...

Page 70: ...nd functions COMPLEMENT A quantity expressed to the base N which is derived from a given quantity by a particular rule frequently used to represent the negative of a given quantity A complement on N o...

Page 71: ...its past or present input signals AND gate or OR gate HALF SUBTRACT The bit by bit subtraction of two binary numbers with no regard for borrows abbreviated H The complement for half subtrac t is half...

Page 72: ...r attention JUMP An instruction or signal which conditionally or unconditionally specifies the location of the next sequential instruction and directs the computer to that instruction used to alter th...

Page 73: ...of a number NONADDRESSABLE Pertaining to a storage location incapable of being referenced by an instruction word NONDESTRUCTIVE READOUT A memory device that stores information which has been preset a...

Page 74: ...number of ones contained in a given word or group of words or instructions PASS A complete cycle of reading processing and writing A complete machine operation or run PERIPHERAL EQUIPMENT Auxiliary ma...

Page 75: ...structions or functions capable of being executed by the computer repertoire of instruction See definition of instruction repertory RESET To clear to set to zero to return a device to zero or to an in...

Page 76: ...icant digit whose value is known and considered relevant SINGLE ADDRESS CODE Consisting of instructions containing a coded representation of the operation to be performed and a single address of a wor...

Page 77: ...GENERAL DESCRIPTION Figure 1 19 Figure 1 19 Printed Circuit Module Type A ORIGINAL 1 61...

Page 78: ...Figure 1 20 GENERAL DESCRIPTION Figure 1 20 Printed Circuit Module Type B 1 62 ORIGINAL...

Page 79: ...nverter 26 25 9 8 8 Inverter 6 3 10 37 2 Inverter 10 10 19 35 16 Inverter 19 19 58 8 34 Inverter 15 14 27 16 14 Inverter 1 1 4 1 2 Input Amplifier 44 4 3 Driver Amplifier 3 Driver Amplifier 1 Driver A...

Page 80: ...21 12 6 2 Capacitor Assembly 5 5 7 7 7 7 Time Delay 4 4 Driver Amplifier 1 2 Regulator Amplifier 1 Memory Driver 9 Pulse Delay Network 3 Emi tter Follower 1 4 Driver Amplifier 4 Transformer Driver 4 P...

Page 81: ...LE COMPLEMENT PART NO DESCRIPTION MEMORY CAPACITY 16K 32K 48K 7500040 Driver Amplifier 3 4 7 7500260 Oscillator Delay Line 1 1 2 Amplifier 7500280 Emitter Follower 1 1 2 7500340 Voltage Sensor 1 1 2 7...

Page 82: ...s additional 16K F12 F13 F14 4 16K 1 amp additional 16K F15 F16 Fl7 2 8 I O 1 amp additional 8 I O TABLE 1 19 POWER CONTROL SWITCHES AND RELAYS RELAY OR SWITCH DESIGNATOR NAME FIGURE NO PSIKI Power co...

Page 83: ...ng crate STEP 2 Lift off and remove top section of the crate STEP 3 Pry loose and pull away four sides of crate to expose equipment STEP 4 Remove all packing material such as shredded paper from aroun...

Page 84: ...heral equipment unless a given application requires otherwise The maximum distance between a peripheral device and a computer with the slow interface option is 300 feet when the signal cables used are...

Page 85: ...I III III III III Llj rrl I III III II 1lI 26 75 III CHASSIS I I I EXPANSION III III LJ J n I I WAll I I II I 11 FLOOR _ L_ _ _I SIDE VIEW 1 o o 26 2 I 4 DRAWER UNIT FRONT VIEW L 10 0 r 1 1 l BOTTOM V...

Page 86: ...Figure 2 2 I STALLATION Q s C O J t c r s W Q 0 C O U 0 rn rn Q 0 s C O s 0 C O 0 J N I N Q Ol c 2 4 ORIGINAL...

Page 87: ...C 03 STEP 4 Connect the other end of the cable to the designated terminals at the control panel STEP 5 Verify all connections at A14Jl and at the power supply STEP 6 Perform the initial power checks...

Page 88: ...G HOLES 1 USE 13 BOLTS FOR MOUNTING o AI2EI BACK VIEW i I I BOTTOM VIEW 6 38 DIA FOR 18 SCREWS 3 a 16 UNC GROUND STUD 67 56 AIR EXHAUST IT 3 52 t I i 8 72 17 44 l Figure 2 3 Location of Cabinet Mounti...

Page 89: ...nnel 3 output J30 Channel 16 output J12 Channel 2 output J31 Channel 15 output Jl3 Channel I out put J32 Channel 14 output J14 Channel O output J33 Channel 13 output J15 Channel 7 input J34 Channel 12...

Page 90: ...Spare R External function request R 15 232 R 232 R 16 233 R 233 R 17 234 R 234 R 18 235 R 235 R 19 20 R 20 R 20 21 R 21 R 21 Not used Not used 22 22 22 23 23 23 24 24 24 25 25 2 5 26 26 26 27 27 27 2...

Page 91: ...ON Not used 2 13 214 2 15 2 16 217 18 2 2190 20 2 2 21 222 223 213CR 214 R 2 15 CR 216 CR 217 R 218 R 2 19 CR 220 R 2 21 CR 222 R O 223 CR Cable shield 24 2 25 2 226 2270 28 2 29 2 30 2 2310 Not used...

Page 92: ...for 36 bit word equipment these pin designations apply When the computer is operating single channel for 18 bit word equipment pin designations do not apply Pins labeled with an asterisk are considere...

Page 93: ...inal Check indicator Horn Alarm Stop 5 indicator Unas signed Unassigned Unassigned Unassigned Unassigned Unassigned Unass igned Stop 1 indicator Run indicator Remote indicator Stop 4 indicator Stop 3...

Page 94: ...Skip 4 switch Skip 3 swi tch Skip 2 switch Skip 1 switch Skip 0 swi tch Master clear switch Stop 4 switch R Stop 3 switch R Stop 2 switch R Stop 1 switch R Stop 0 switch R Skip 4 switch R Skip 3 swi...

Page 95: ...ug A12El along with all internal circuit grounds Use a separate cable for grounding each peripheral device to the computer These cables should not be junctioned at any point other than at the ground l...

Page 96: ...ER I I I I I I 1 EI COMPUTER E3 E2 I O CABLE r I 1 1 I I 1 I PERIPHERAL PERIPHERAL PRIMARY POWER GROUND SO CPS GROUND 400 CPS NEUTRAL 400 CPS POWER 400 CPS POWER MOTOR I GENERATOR I TO PRIMARY POWER F...

Page 97: ...r retaining bolt Use combination tool and unscrew drawer retaining bolt until plugs on rear of drawer are disengaged from cabinet receptacles Slide drawer forward to fully extended position and ensure...

Page 98: ...mate Center Neutral Down Down Down Down Down Down Down Down Normal Normal NDRO Located behind front panel on drawer A2 STEP 5 STEP 5A STEP 5B STEP 5C 2 16 On computer s power control panel set POWER s...

Page 99: ...EP 6 STEP 7 STEP 8 STEP 9 CHANGE 3 GRILL Figure 2 4A Blower Rotation Check Press MASTER CLEAR switch to clear computer logic circuitry Press PHASE STEP MODE switch to place computer in phase step mode...

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Page 101: ...16 5 0 20V 15V TBl TP E33 13 5 to 16 5 0 20V 4 5V TBl TP F33 4 05 to 4 95 0 20V Ground TBl TP G33 VOLTAGE TEST BLOCK DRAWER A4 TOLERANCE DC RIPPLE Peak to Peak 7V regulated TB2 TP A33 15V regulated T...

Page 102: ...Figure 2 5 TEST POINTS INSTALLA nON Figure 2 5 Test Point Card 2 18 CHANGE 2...

Page 103: ...ESHIPMENT To prepare for reshipment perform the following steps CAUTION Before proceeding with step 1 check to ensure power is OFF at the computer and the control panel or junction box STEP 1 STEP 2 S...

Page 104: ...ing skid and bolt cabinet securely in place on skid STEP 10 If computer is being prepared for overseas shipment place computer in a plywood crate filling airspace between crate and cabinet with shredd...

Page 105: ...The indicators provide a visual indication of status and operation they are intended primarily for maintenance personnel 3 2 DESCRIPTION OF C N1ROLS Tables 3 1 through 3 4 list the switches and indica...

Page 106: ...ressing above indicator switches except CHAN PRI will set associated flip flops Indicator switches indicate function and channel group of that coordinate Odd numbered I O channels Even numbered I O ch...

Page 107: ...ROL PANEL 1 A2 TITLE FUNCTION USE 0 17 and Clear 0 17 and Clear ICR 0 2 and Clear Index Control Register SR Special Register ORIGINAL Bits 0 3 and Clear ACT Displays contents and allows manual con tro...

Page 108: ...tes performance of second R read sequence Indicates performance of W write sequence Indicates performance of WAIT sequence For example computer waits for an interrupt Indicates performance of first B...

Page 109: ...r modes and enables PHASE indicator switches and computer for clock phase operatio Inhibits memory Indicates operation step mode Pressing MODE OP STEP button sets operation step mode clears all other...

Page 110: ...on START STEP Load mode selected initiates high speed start at address 00500 Run mode selected initiates high speed start at address designated in p Phase step mode selected initiates issuance of phas...

Page 111: ...OPERATOR S SECTION Figure 3 1 Figure 3 1 Input Output Panel AI or optional A8 ORIGINAL 3 7...

Page 112: ...Figure 3 2 OPERATOR S SECTION r mall r M If I b I h If ttl Figur e 3 2 Control Panel 1 A2 3 8 ORIGINAL...

Page 113: ...ol of 18 bits of main memory exchange register Each bit may be set by pressing appropriate indicator switch Press ng Clear button clears all 18 bit positions Displays contents and allows manual contro...

Page 114: ...y be received Indicates that operation of updating real time clock word is in process Up position RTC interrupting signal is disconnected disabled Down position RTC interrupting signal is operational...

Page 115: ...en tari ly in ON position power is applied to computer in momentarily OFF position power is removed Proper interlock and operating temperatures POWER Indicator Comes on when power is being applied to...

Page 116: ...Figure 3 3 OPERATOR S SECTION NOTE TEST BLOCKS INSTALLED ONLY ON SN 14 48 Figure 3 3 Memory Panel A3 3 12 CHANGE 2...

Page 117: ...OPERATOR S SECTION Figure 3 4 Figure 3 4 Control Panel 2 A4 ORIGINAL 3 13...

Page 118: ...Figure 3 5 3 14 OPERATOR S SECTION ORIGINAL i o C o U CI l o 0...

Page 119: ...ragraphs 3 4 thru 3 5 When instructed to press SWITCH A to XX the momentary toggle switch marked SWITCH A is to be pressed to the position marked XX and released When instructed to press SWITCH A the...

Page 120: ...EP STOP switch to STOP Press I O CLEAR MASTER CLEAR switch to MASTER CLEAR Set the P register equal to one less than the address of the desired storage address Set the FUNCTION CODE register equal to...

Page 121: ...or bootstrap program The computer can have a bootstrap written for paper tape magnetic tape or teletype input The following paragraphs describe the paper tape bootstrap as a typical example The wired...

Page 122: ...kages and utility packages for use by the programmer and or operator are available with the 1219B computer These packages facilitate the writing and operation of programs For a complete analysis of th...

Page 123: ...nts of a register Designates the contents of two consecutive memory locations linked together to form a 36 bit word Address Y l contains the most significant half of the word while address Y contains...

Page 124: ...memory reference however u is extended to 18 bits See list of instructions b u USED AS AN ADDRESS For this case u is used 12 bits of the base address referring to a memory location 16 bits designated...

Page 125: ...more sophisticated use The instructions are listed and defined in the following format 1 Octal code Instruction name TRIM code Symbolic summary 2 Execution time 3 Definition of the y address or consta...

Page 126: ...quent instruction other than codes 60 67 and no interrupt is honored while the designator is set 04 05 06 SELECTIVE SUBSTITUTE SLSU L AU AL L AU Y AL or Y n ALn for AU n 1 Execution time 4 microsecond...

Page 127: ...222351 Compare 2351 with 3451 AU f 007777 AL f 222351 COMPARE WITH MASK CCMSKB Execution time y up or uSR L AU AL AU Y 4 microseconds Algebraically compare selected bits of AL with corresponding bits...

Page 128: ...uSR Add y B to AL and leave the result in AL Set overflow designator if overflow occurs AL f are all ones if AL i and y B are all ones SUBTRACT AL SUBAL AU Y AL Execution time 4 microseconds y up or u...

Page 129: ...d correction Only add A or subtract A instructions set the designator 21 22 Example of a double add with y 07506 A 1 Address 07506 Address 07507 A f ADD A ADDAB Execution time y up or uSR 201007430145...

Page 130: ...gous to the add A instruction See note instruction 20 MULTIPLY AL MULAL AL x Y A Execution time 14 microseconds y up or uSR Multiply AL by y leaving the double length product in A If the factors are c...

Page 131: ...nce register on interrupt y u Store P at the address which then increment that address by program address register Example of an indirect return Initial Final Address Contents Contents 22000 30 6500 S...

Page 132: ...econds The full 18 bits of y are transmitted to the B register a normally addressable memory location ENTER B ENTBB Execution time y up or uSR Transmit y B to BICR Y B Reg 4 microseconds The full 18 b...

Page 133: ...extended to 18 bits Bi xY B Reg 2 microseconds Add y to B add a constant to B Note that u is a 12 bit one s complement number contained within the instruction and can be used to increment or decrement...

Page 134: ...age address y B AU f AU i CAL Y 4 microseconds AU Y 4 microseconds AU Y 4 microseconds 4 microseconds 50 See format II instructions immediately following function code 77 51 52 SELECTIVE SET SLSET Exe...

Page 135: ...AL for y 1 This is a bit by bit exclusive OR n n Example of selective complement instruction AL 123456 1 y 070007 AL f 153451 INDIRECT JUMP AND Y P enable interrupts ENABLE INTERRUPTS I JPEI Executio...

Page 136: ...arison designator is set Otherwise execute next instruction JUMP AL ZERO JPALZ JPEQ Execution time y up If compare AL oJ compare AL M 0 L AL AU Y P 2 microseconds JUMP to y for example set P y if 1 Co...

Page 137: ...p If compare AU Pos G compare AL Me L AL AU M Y P 2 microseconds Jump to y for example set P y if 1 Compare stage of comparison designator is not set and AU O or 2 Compare stage of comparison designat...

Page 138: ...ME LC AL AU M Y P 2 microseconds Jump to y for example set P y if 1 Compare stage of comparison designator is not set and AL O or 2 Compare stage of comparison designator is set and the greater stage...

Page 139: ...bits of y with a six bit value consisting of the four lower order bits equal to the contents of the index control register and the remaining two bits equal to zero As this instruction affects a six bi...

Page 140: ...oes not clear the other 4_bits 76 DIRECT RETURN JUMP RJP Execution time y u P PHI Y Y l P 4 microseconds Store P l at y then jump to y l This instruction transfers to y a full 18 bit word the lower bi...

Page 141: ...xecution time 2 microseconds Set channel k external function mode active The buffer control words stored in memory locations 20 2k and 21 2k channels 0 7 or 220 2 k 10 and 221 2 k 10 channels 10 17 wi...

Page 142: ...2 microseconds Enable the real time clock monitor interrupt ignore k After execution of this instruction equality between the RTC word register location 15 and the RTC monitor word register location...

Page 143: ...IVE SKPEIN Execution time 2 microseconds skip or no skip Test for external function activity on channel k If inactive skip the next instruction otherwise take the next instruction 50 24 WAIT FOR INTER...

Page 144: ...1 Execution time 2 microseconds Remove the interrupt lockout enable all interrupts all channels ignore k NOTE A 50 30 or 50 31 instruction must be used in conjunction with a 50 34 or 50 35 instruction...

Page 145: ...ft 700000 50 42 RIGHT SHIFT AL RSHAL Execution time Same as instruction 50 41 Shift AL to the right k bit positions The higher order bits are replaced with the original sign bit AL17 as the value is s...

Page 146: ...A I After first shift 600000 000000 negative not normalized 400000 000000 negative normalized The computer then stores the quantity 000002 00017 3 Example of scale factor with k 1 A i After first shif...

Page 147: ...40 bit 5 k 03 bits 1 0 Skip if skip key uO is set Skip if skip key ul is set Skip if skip key U2 is set Skip if skip key u3 is set Skip if skip key u4 is set Skip unconditionally Skip if either key ul...

Page 148: ...SKPEVN Execution time 2 microseconds skip or no skip If the sum of the bits resulting from the bit by bit product of AL and AU is even skip the next instruction otherwise take the next instruction Ign...

Page 149: ...be a double length value in A is normalized as far as possible to the left however only a rounded single length number is required for the accuracy desired 50 61 COMPLEMENT AL CPAL AL AL Execution ti...

Page 150: ...index control register Then transmit the three low order bits of k to the ICR 50 73 ENTER SPECIAL REGISTER ENTSR k4 0 SR Execution time 2 microseconds Clear the special register Then transmit the five...

Page 151: ...of specific sequencing and enables allows computer operation under either manual or program control During manual operation circuit conditions are displayed on the front panels of the logic drawers Th...

Page 152: ...NTROL PANEL START STOP LOGIC MASTER CLEAR REMOTE CONTROL MODE SELECT LOGIC TIMING CIRCUITS MASTER CLEAR MAIN TIMING CYCLE REGISTERS INDEX REG ICR tEG SR REG P REG 51 REG SO REG K REG PROGRAM TRANSLATI...

Page 153: ...earing the run flip flop In run mode this is accomplished by programmed stops or by manually setting the SEQ STEP STOP switch to STOP position In the op step mode the run flip flop is cleared and comp...

Page 154: ...speed operating mode of the computer All operations not pertaining to malfunction isolation and program de bugging are performed in run mode Although initial program loading is performed in the load...

Page 155: ...LEAR FUNCTION REPEAT PHASE 0 0 2 0 SEQ STEP STOP PHASE REPEAT 0 I 0 LOAD 0 RESTART SPEED CONT AUTO RECOVERY MODE 0 PHASE STEP 0 OP STEP Figure 4 2 0 RUN RESTART START STEP DISC ADV P Figure 4 2 Operat...

Page 156: ...SI4D i J OOJ03 OOJ02 L L L L L L Q 1 1 t Q 0 t OIJOI PHASE PART OF STEP DSI4C i J OOJOI L L L THEORY OF OPERATION H Z III t OIJOO OP PIlRT OF STEP DSI4B r i J OOJOO L L L RUN PART OF DSI4A G I fJ Figu...

Page 157: ...computer high speed run Normal high speed run with bootstrap memory Repeat instruction contained in F register for each momen tary operation of RESTART START STEP swi tch Stop computer high speed ope...

Page 158: ...cycle The relationship between the phases clock cycles and computer cycle is illus trated in figure 4 4 This illustration also includes the relationship of timing chain outputs to the master clock out...

Page 159: ...e outputs to clock pulses The auxiliary timing chain in figure 9 36 is discussed in paragraph 4 2b d PHASE STEP LOGIC Phase step logic figures 9 3 and 9 4 enables the operator to apply either single s...

Page 160: ...I 3 I 4 I I 2 I 3 I 4 I I 2 I 3 I 4 Til 11 LOW Tl2 a T52 HIGH J Tl3 I TI4 T21 I T22 I J l 0 I T23 0 0 0 T24 J u 0 I i T31 u z T32 I r C z I T33 z T34 T41 I T42 L T43 I T44 SHADING INDICATES THE UNUSA...

Page 161: ...EVEN PHASE FLIP FLOP ODD PHASE GENERATOR ODD PHASE FL IP FLOP EVEN PHASE GENERATOR Figure 4 5 Master Clock Logic Simplified Diagram CHANGE 2 4 11...

Page 162: ...4 6 OUT1 UT FROM ODD PHASE GENERATOR EVEN PHASE GENERATOR EVEN PHASE fliP flOP ODD PHASE FLIP FLOP THEORY OF OPERATION I I I I I I I I I I I I I I 1 _I Figure 4 6 Master Clock Output Signals 4 12 ORI...

Page 163: ...ures 9 41 through 9 48 to be used for sequencing and control of computer logic By placing the FUNCTION REPEAT switch in the up position both the clear enable and transfer enable of the F register are...

Page 164: ...completed The selection of the required sequences and the order of their performance is determined by the translation data applied to the sequence designator circuitry figures 9 12 and 9 13 1 UPPER R...

Page 165: ...0 II lLI II II If 11 N 11 11 fi J It J J J 91F04 42F20 L L X N ID X 0 ti It lLI N 2 x t x If I It I V 0 0 ID 10 N N 10 LL X 2 x II II II II It II II II II 11 fi 11 1l ft ft ft ft x J J J J J J J J Fig...

Page 166: ...outputs are gen erated by the gating of several control signals and are identified as to their function by the signal description term 2 II 12 and INTERRUPT SEQUENCE OUTPUTS The II 12 and interrupt s...

Page 167: ...register control circuit figure 9 20 provides enableS required by the AU and AL registers to effect transfer of information either into or from these temporary storage locations These enables are prod...

Page 168: ...GISTER CONTROL The P and B register control circuit figure 9 21 supplies through gating transfer and clear enables for the P and B registers The B register is represented on the block diagram of figur...

Page 169: ...ICR and SR reg isters These enables are the product of gating function code translation se quencing commands and timing signals Circuit output signals and their functions are listed as follows H CLEAR...

Page 170: ...in memory Enables transfer of the contents of the adder to the 21 register for storage in memory Enables transfer of the contents of the 21 register to the 20 register for storage in control memory En...

Page 171: ...UPPER L I O EVEN UPPER L I O ODD LOWER L I O EVEN LOWER L I O Enables transfer of the contents of the C register associated with I O channels 11 13 15 and 17 to the store select circuit Enables transf...

Page 172: ...pulses The enables and their functions are listed below 4 22 L FORWARD L 1 B L 1 B L BACKWARD L MULTIPLIER STORE L INHIBIT EAB L INSERT EAB L ALL INTERRUPT LOCKOUT L LOCKOUT EXT INT H HOLD 1 Indicates...

Page 173: ...ion of the computer Included in this category are the ICR reg ister SR register K register KI and KO counter register and B register Each of these registers perform a logic control function not necess...

Page 174: ...ork primarily increments or decrements the buffer control word and also is used to specify the memory address to be used during an ESA operation Inputs to the B register are routed from either the Zo...

Page 175: ...TION Figure 4 9 1 SET BITS TO BE USED SR REGISTER FOR ADDRESS ACTIVE EXTENSION r r A BIT BIT BIT BIT BIT 2 2 22 21 20 J Y t I A l y Jl_ Y T L 7 NOT USED 50 igure 4 9 Bit Content Activate SR Instructio...

Page 176: ...ve If there is no EAS when signs are unequal the value in the X register must be equal or greater than the quantity from memory A Y If there is an EAS and signs are equal then the value in the X regis...

Page 177: ...al instruction in the program If these conditions are not satisfied the computer executes the next sequential programmed instruction in the normal manner Par agraph 3 6 includes stop and skip instruct...

Page 178: ...I O channel is used whenever the channel is connected to another computer figure 4 11 The intercomputer class of operation subordinates the sending computer to the receiving computer Cables used to c...

Page 179: ...EVICE I I INPUT DATA REQUEST INPUT I INPUT ACKNOWLEDGE L_ INPUT DATA 18 COMPUTER CHANNEL 1 r i o EXTERNAL FUNCTION REQUEST I EXTERNAL FUNCTION ACKNOWLEDGE I OUTPUT DATA REQUEST OUTPUT I OUTPUT ACKNOWL...

Page 180: ...NE I INPUT OUTPUT DATA I ACKNOWLEDGE REQUEST I I L INPUT DATA OUTPUT DATA I 18 J COMPUTER COMPUTER CHANNEL CHANNEL EXTERNAL h FUNCTION r 1 REQUEST NC I EXTERNAL EXTERNAL I FUNCTION INTERRUPT I I AC KN...

Page 181: ...__ PERIPHERAL DEVICE USING 36 BIT DATA I WORDS IOUTPUT I L __f r h CONTROL 0LINES I INPUT INPUT DATA I 18 I INPUT DATA L __ 1 r I 0 CONTROL LINE S I OUTPUT 1 OUTPUT DATA I I 18 OUTPUT DATA L __ 000 NU...

Page 182: ...cond half for interrupt requests Sequence timing tables list the commands and conditions for each sequence and in the case of the I O sequences the mode of operation is given I O sequences I O 1 and I...

Page 183: ...T4 2 ORIGINAL data request was scanned up CLR Chan and Function Priority In t Req Chan Priori ty CLR Xlator 1 Channel and Function Xlator f k to Xlator 1 Channel and Function Xlator In t Req Function...

Page 184: ...34 IS CHAN ACT VE FOR 10 YES TRIGGER 10 REQ ONE SHOT SEND ADDRESS OF CABCW TO SO REG TRANSFER CABCW FROM MEMORY TO BU REG ADD 1 TO CABCW RETURN CABCW TO ITS CONTR MEMORY LOCATION NO THEORY OF OPERATIO...

Page 185: ...YES SEND CABCW 1 TO ZO REG WRITE NEW CABCW IN CONT HEM YES THEORY OF OPERATION RESET 10 REQ ONE SHOT CMD DESIGNATOR SET YES SET CMO REQ FF YES DATA SEQ ODD CHAN IN PUT TO ZO OR Z1 REG NO IF MON BIT I...

Page 186: ...INT AFTER 2 2 USEC SLOW INT AFTER 8 0 USEC ORIGINAL Figure 4 15 SET EI MON FF SET EI HON CONT FF SET ALL INTERRUPT LOCKOUT FF INITIATE INT SEQUENCE SEND ADDRESS TO S1 REG READ FROM EVEN EI ENT ADD RE...

Page 187: ...D INMEM PLACE INPUT ACK ON CONTROL LINES DROP ACK FAST INT AFTER 2 2 USEC SLOW INT AFTER 8 0 USEC THEORY OF OPERATION INITIATE INT SEQUENCE SEND ADDRESS TO S1 REG SET EI MON CONT FF SET ALL INTERRUPT...

Page 188: ...T AFTER 8 USEe TRIGGER 00 REQ DOES THIS CHAN AND FUNC HAVE PRIORITY YES SEND ADDRESS OF CABCW TO so REG TRANSFER CABCW FROM MEMORY TO BU REG ADD 1 TO CABCW Figure 4 17 NO SET COM SEQ CLR BIT 0 OF SO R...

Page 189: ...SO 2 0 Bu Sl I O Xlator Sl Set Sl 20 and 26 Enable Main Memory B 1 ZO CLR Zl CLR ID Active FF Set EI Monitor Set Monitor FF if Monitor bit set SINGLE Not EI Not EI x x x Not EI x Not EI Not EI x x x N...

Page 190: ...emory 20 Zl or ZO Z SELECT Z SELECT C SINGLE OD EF Termi na 1 L CDM OD EF OD EF IDIEI OD EY IDIEI x x x OD EF CDM REQ SET ID OD EF and SO OD EF OD EF DUAL OD EF Termi na iL CFM OD EF OD EF IDIEI even...

Page 191: ...r II x x Set B l Oesig 1 if bkwd buffer bit set x x T4 3 Con trol Memory ZO Not EI CLR Resume FF OO EF OO EF Set Input Ack Register IO EI IO EI CLR IO EI Req FF IO EI IO EI T4 4 Terminate BU ZO x Set...

Page 192: ...chan if fwrd if bkwd odd if even chan bkwd if frwd Start OD EF Ack Timing OD EF OD EF 1 2 1 Start IDIEI Ack Timing ID EF ID EF Sl SO if Sl CM address x x Initiate CM if CM x x CLR ZO if CM address x...

Page 193: ...2 Tl 3 T1 4 T2 1 T2 2 T2 3 Xlator SO Set SO 20 Initiate Control Memory CLR ZO CLR Bu Control Memory ZO Xlator SO Set SO 20 Initiate Control Memory Inhibit Clear ZO Inhibit Control Memory ZO Xlator SO...

Page 194: ...CABCW 1 TO ZO REG YES THEORY OF OPERATION CHD DESIGNATOR SET YES SETCHO REQ FF 00 ACK ENABLED YES INITIATE COIIf DATA SEQ RESET OD RI Q ONE SHOT TRANSFER 00 WORD FROM MEMORY TO Zl OR ZO REG IF MON BI...

Page 195: ...NE SHOT SEND ADDRESS OF CABCW TO SO REG TRANSFER CABCW FROM MEMORY TO BU REG ADD 1 TO CABGW RETURN CABCW TO ITS CONTR MEMORY LOCATION NO CLR BIT 0 OF SO REG ADDRESS OF TABCW TRANSFER TABCW FROM MEMORY...

Page 196: ...B Designator to 1 CLR ZO T4 2 Set I O 1 FF Upper Rank T4 3 Control Memory ZO T4 4 T1 1 T1 2 T1 3 Set Terminate FF Xlator SO Set SO Initiate Control Memory Set Resume fault CLR ZO B 1 ZO Set RTC Monit...

Page 197: ...1 OR ZO REG IF MON BIT IN CABCW SET SET EF MON FF NO PLACE EF WORD IN BOTH OUTPUT REGS YES OPERATION DUAL YES IS BUFFER FORWARD I O 1 SEQUENCE PLACE EF WORD III EVEN OUTPUT REG ESI CONDITION PLACE EF...

Page 198: ...ERNAL FUNCTION REQUEST TO COMPUTER OUTPUT DATA BIT OR EXTERNAL FUNCTION CODE BIT FROM COMPUTER OUTPUT ACKNOWLEDGE OR EXTERNAL FUNCTION ACKNOWLEDGE FROM COMPUTER Figure 4 21 OV f 0 0 USEC 15V tv2 4 15V...

Page 199: ...TION REQUEST TO COMPUTER THEORY OF OPERATION r OV 0 0 USEC 0 8 USEC OV 3V OV 3V INPUT COHHUNICATION OV 3V 2 7 USEC 1 0 0 USEC OUTPUT DATA 81T OR EXTERNAL FUNCTION CODE BIT FROM COMPUTER E E 3 2 USEC _...

Page 200: ...composed of five flip flop registers a subtractive type adder and a logic selecting circuit The arithmetic section performs the following arithmetic operations add subtract multiply divide shift and...

Page 201: ...TION ARITHMETIC SELECTOR 1 THEORY OF OPERATION CONTROL P SR REGISTER REGISTER I I ______ X REGISTER AU REGISTER ADDER SUB TYPE p s a z REGISTERS D REGISTER AL REGISTER W REGISTER Figure 4 23 Arithmeti...

Page 202: ...xecution of double length 36 bit shift instructions 6 Has shifting properties when used in conjunction with the X register 7 Holds mask during certain logical operations Inputs to the AU register are...

Page 203: ...tract operation and the difference after subtraction 3 Stores least significant IS bits of the augend prior to a 36 bit add operation and the least significant IS bits of the sum after addition 4 Stor...

Page 204: ...simplified diagram of these transfers and command enables under which they are executed Output to the arithmetic se lector is a direct transfer of bits in the AL register to the corresponding bits in...

Page 205: ...separate and distinct operations One operation will either load or transfer the contents of AL the other will either load or transfer the contents of AU 4 D REGISTER D register figures 9 85 and 9 86 i...

Page 206: ...lector to be entered into X Outputs from the X register are applied to the AU register during shifting se quences as stated above and to the adder and adder borrow enable generation cir cuits The outp...

Page 207: ...flop circuits and its contents are not visually displayed on the front panel Figure 4 26 illustrates a typical stage of the arithmetic selector Inputs to this stage are actually the complement of the...

Page 208: ...lJXXX l 3XXX l z II Ll L AU SELECT L AL SELECT L Z SELECT L P SELECT L SR ICR K SELECT 0 0 en x N X x lo N N X 0 ID N J X l N ID ID I en ID J C C N Q ID Figure 4 26 Typical Stage of Arithmetic Selecto...

Page 209: ...ame output of the 10A circuit will be a high zero if they are opposite this output will be a low one Therefore this output is a half subtract result with no regard for borrows Output of the llA circui...

Page 210: ...THEOijY OF OPERATION o o 0 o 0 L X 0 0 o o 0 Figure 4 27 Single Stage of Half Subtractor Figure 4 27 ORIGINAL 4 63...

Page 211: ...ivision are performed fol lowing the rules of signed arithmetic Multiply and divide operations have been reduced to a series of additions and subtractions and are executed as such through the computer...

Page 212: ...THEORY OF OPERATION Figure 4 28 4 z H BORROW TO N L BORROW TO N 12A Figure 4 28 Single Stage of Borrow Generator ORIGINAL 4 65...

Page 213: ...to the D register Complement of the minuend is then added to the subtrahend to produce the arithmetic difference which is then stored in the AL register The flow chart figure 4 30 illustrates the exe...

Page 214: ...DDER UPPER 18 BITS OF ADDEND IN AU AU SELECT FIRST SECOND 1 FI RST OR SECOND PASs 1 0 LOWER 18 BITS OF AUGEND YJ MEHORY X FIRST ADDER AL Z SELECT SELECT D D ADDER UPPER 18 BITS OF AUGEND Y 1 J MEHORY...

Page 215: ...OF MINUEND IN AU AU SELECT FIRST SECOND 1 FI RST OR SECOND PASS t LOWER 18 BITS OF SUBTRAHEND YJ MEMORY Z FIRST 2 2 2 Z SELECT D ADDER UPPER 18 BITS OF SUBTRAHEND Y 1 J MEMORY Z SECOND r FIRST OR SEC...

Page 216: ...he divisor from the dividend Each subtraction attempt is followed by a one place left shift of the contents of A register K register contents are decremented by one and a test is performed to determin...

Page 217: ...K1 DOES Kl 0 NO AUR1 X ALR1 W DOES AL20 NO Kl KO X AU W AL 1 POSITIVE VALUE MULTI PL ICANO o THEORY OF OPERATION YES CONVERT VALUES OF l AU AL IF NECESSARY YES SET MULTIPLIER STORE FLIP FLOP 1 Kl KO 2...

Page 218: ...ter is used in conjunction with AL register The X and W registers are combined when used with the A register 1 SHIFT AU Right and left shift AU instructions f 50 41 and 50 45 use AU and X registers to...

Page 219: ...AU BIT O UE 2 1 2 3 2 3 1 3 2 START SET KO 1810 KO 1 Kl DOES Kl 0 YES NO AUL1 X ALL1 W END AROUND NO BORROW YES Kl KO 1 X AU W AL Figure 4 32 Divide Sequence THEORY OF OPERATION NEGATIVE VALUE DIVISOR...

Page 220: ...additional timing chain output T52 is developed for complement instructions involving the AL register The adder contents are transferred to the AL register without requiring the use of the normal timi...

Page 221: ...1 Oil I 1 1 0 1 Oil 17 16 15 1 02 01 00 STEP X AU 02 RIGHT SHIFT AU x AU X AU X AU X AU THEORY OF OPERATION 17 16 15 1 02 01 00 I_o__o __ o __ o ___ 0__0 __0 1 17 16 15 1 02 01 00 11 0 1 1 0 1 0 I QUA...

Page 222: ...OPERATION QUANTITY IN AU NO Figure 4 34 ORIGINAL CLEAR K1 CLEAR X KO 1 K1 AUL1 OR R1 X CLEAR KO K1 KO CLEAR AU X AU K1 SHIFT COUNT IN KO fl2 fl 3 fl1 02 Shift Commands and Functions AU Register Figure...

Page 223: ...1 02 01 00 I 1 1 0 1 o 11 1 0 1 o 11 17 16 15 1_ 02 01 00 w AL W AL W AL 17 16 15 1 o 000 17 16 15 1_ 1 0 1 1 QUANTITY IN AL STEP 1 CLEAR W 03 17 16 15 1 17 16 15 1 02 01 00 o 0 0I 02 01 00 0 1 01 02...

Page 224: ...F OPERATION QUANTI TV I N AL NO CLEAR K1 CLEAR W KO 1 K1 ALR1 W OR ALL1 W CLEAR KO K1 KO CLEAR AL X AL SHIFT COUNT IN KO 02 01 02 Figure 4 36 Shift Commands and Function AL Register Figure 4 36 ORIGIN...

Page 225: ...02 01 0 0 02 01 00 11 01 00 00 1 I 1 1 00 W AL W AL W AL THEORY OF OPERATION 35 3 33 18 17 02 01 00 I0 oI x 0 0 0 0 0 0 0 W QUANTI TY IN A 11 oI AU 0 1 0 1 0 1 AL 35 3 33 18 17 02 01 00 STEP 1 CLEAR x...

Page 226: ...HIFT COUNT IN KO CLEAR K1 2 CLEAR X 3 CLEAR W KO 1 K1 3 LEFT SHIFT 1 RIGHT SHIFT 1 0 ALL1 W ALR1 W 0 AUL1 X AUR1 X 0 CLEAR KO CLEAR AL 01 CLEAR AU K1 KO 01 W AL X AU NO K1 O YES 7 Figure 4 38 Shift CO...

Page 227: ...erased during the read cycle and a word may not be written into this memory However provisions have been incorporated to store two bootstrap programs that is load routine for paper tape and load routi...

Page 228: ...STEP 2 X ADDER 0 3 4J 0 0 0 o 0 0 I D STEP 4 CLEAR D 04 3 17 16 15 02 01 00 10 1 1 1 1 o 1 D 1 0 0 0 0 1 1 ADDER 17 16 15 02 01 00 STEP 6 D ADDER HALF SUBTRACT 04 4 Figure 4 39 Complement AL ORIGINAL...

Page 229: ...F OPERATION QUANTITY IN AL I SEQUENCE FORMAT 2 3 SELECT X SET X 1 S SELECT X 3 X ADDER 2 AL SELECT 3 CLEAR 0 SELECT D D ADDER 5 1 CLEAR AL 5 2 ADDER AL Figure 4 40 Complement AL Instruction Command Se...

Page 230: ...THEORY OF OPER TION QUANTITY IN A 1 2 CLEAR 0 AU SELECT SELECT X SELECT X SITffi D CLEAR AU ADDER AU Figure 4 41 Sequencing of Complement AU Instruction 50 62 Figure 4 41 ORIGINAL 4 83...

Page 231: ...TION QUANTI TV IN A 3 3 CLEAR D 3 AU SELECT SELECT X SELECT X SELECT D 1 CLEAR AU 2 ADDER AU 3 AL SELECT CLEAR D SELECT D D ADDER 5 1 CLEAR AL 5 2 ADDER AL Figure 4 42 Sequencing of Complement A Instr...

Page 232: ...THEORY OF OPERATION MEMORY STACK 4K TYPICAL I OF 8 Figure 4 43 Main Memory Location Drawer A3 A2 Figure 4 43 CHANGE 2 4 85...

Page 233: ...Figure 4 44 THEORY OF OPERATIONS BOOTSTRAP MEMORY CONTROL MEMORY Figure 4 44 Drawer A4 Control And Bootstrap Memory Location 4 86 ORIGINAL...

Page 234: ...s in the core not being switched the core retains the zero that was stored during the read cycle 2 MAIN MEMORY The main memory is a random access coincident current bit oriented core memory with a 2 m...

Page 235: ...ED x x v Poc v STORING 0 STORING I READ WRITE X NO SENSE SENSE PULSE PULSE JI INDUCED V V CORE SENSE SWITCHES INHIBIT TO 0 READING READING CORE HAD A 0 CORE HAD A I SENSE INHIBIT WRITING A 0 WRITING A...

Page 236: ...memory address to be used Bits 15 and 14 of the Sl register are used to select one of four banks figure 4 47 Bits 13 and 12 are decoded to select one of four stacks Bits 11 through 6 are de coded by t...

Page 237: ...ank Heavy lines depict current path for an inhibit pulse to a plane in stack one and the current path for a sense pulse from a plane in s tack two 1 INHIBIT Flip flop 217 figure 4 50 is set by an inpu...

Page 238: ......

Page 239: ...CK 0 STACK 4 4K 4K STACK I STACK 5 4K 4K STACK 2 STACK 6 4K 4K STACK 3 STACK 7 4K 4K I STACK 0 4K STACK I 4K STACK 2 4K STACK 3 4K _J I STACK 4 4K STACK 5 4K too t to t SELECT I OF 4 BANKS 00 SELECT I...

Page 240: ...3 8 THEORY OF OPERATION r WORD SELECT TRANSFORMER 8 SELECT OF 8 LINES IN EACH GROUP STACK 0 EACH Of 64 LINES PASSES THRU A ROW Of 64 CORES ON EVERY PLANE SELECT I Of 8 GROUPS t GROUP I SELECT 1 TRANSf...

Page 241: ...R W L __ J ADDRESS ENABLE BANK SELECT STACK SELECT R W ENABLE BIT 12 f2 BIT 13 i3 15V 4 06 15V GROUP ONE EACH LINE PASSES THRU 18 PLANES 64 CORES PER PLANE READ OR WRITE PRIMARY CIRCUIT 15V CURRENT RE...

Page 242: ...2 HEAVY LINES FROM STACK 2 TO OUTPUT PIN 46 SHOW PATH FOR ONE SENSE PULSE 3 DRAWING ILLUSTRATES SENSE INHIBIT CIRCUITRY FOR A SINGLE BIT ONE OF 18 PLANES 4 ONLY MAJOR COMPONENTS ARE SHOWN REFER TO DES...

Page 243: ...mory stacks Heavy lines in figure 4 50 illustrate current path for an inhibit pulse to stack one and current path for a sense pulse from stack two figure 4 52 is a more detailed diagram showing just t...

Page 244: ...is pulse is recognized as a difference between the two lines by com mon mode rejection transformer T16 Because the two halves of T16 are wound in the same direction current applied from pins Al to A2...

Page 245: ...IS B3 RI5 R21 SV THEORY OF OPERATION RIB RI7 04a 04b 1 5V R22 15V R34 C3 CRIO R3 5 6V 15V R4S all R45 R47 49 R48 50 R52 R 53 05 AND all PROVIDE 013 AND 014 ARE A RECTIFIER FOR FINAL HIGH IMPEDANCE 15V...

Page 246: ...ON CURVE I NHIBIT PULSE CURRENT FROM PIN B7 TO BIO COUNTERACTS BIAS CURRENT AND HOLDS TI OUT OF SATURATION POINT b ON CURVE EXCESSIVE CURRENT FROM PIN B7 TO BIO CAUSES T I TO SATURATE IN A DIRECTION...

Page 247: ...generated by delay line decoding figure 9 135 is gated by bank selection signals figure 9 136 and sent to Zm register input gate as either strobe bank O or strobe bank l If the memory operation being...

Page 248: ...R PHASE INITIATE MEMORY E I DELAY LI NE OUTPUT PI NS ADDRESS ENABLE RE AD READ ENABLE R W ENABLE I 9 13 11 41 53 25 22 R W ADDRESS ENABLE STROBE ENABLE MEMORY Z I CLEAR Zm ADDRESS ENABL E WRITE WRI TE...

Page 249: ...suggested timing Moving connections in the directions indicated by the arrows above delay lines makes a corresponding change in timing shown at the similarly marked points on the time line a ADDRESSIN...

Page 250: ...RD CORE STACK i I t 0 6 0 Q DRIVER DRIVER DRIVER DRIVER l CLR O SET READ WRITE l SET O CLR I I r Il MEMORY CONTROL I so REGISTER Sl REGISTER Figure 4 55 ORIGINAL CONTROL MEMORY ADDRESS DETECTOR T Sl R...

Page 251: ...I READ _____ J A B C D E F C I I l 1 6 8 10 1_ DELAY LI NE 1 tn co z 8 IIJ tn o z c z I IIJ E I THEORY OF OPERATION ENABLE ENABLE WRITE DIGIT 270 SWITCH DRIVERS H 280 H I 290 DISABLE ENABLE STROBE WRI...

Page 252: ...L OUo Z Q O 00 MEMORY c t 0 CD CD 0 CORE I OU o PLANES z Tl 0 1 IV I II EAD 0 READ c READ Q I fE I iI LOWER WORDS UPPER WORDS t t GROUP SELECTORS SELECT 1 OF 8 DIGIT DRIVERS T 1 I U I I I O REylSTE J...

Page 253: ...I o o tI H Cj H r SO REGISTER 8 X 7 X 5 X X 3 X 2 X 1 X 0 X...

Page 254: ...word bit One core is magnetized when storing a binary zero and the other is magnetized when storing a binary one The control memory core plane bit wiring figure 4 60 shows the wiring configuration for...

Page 255: ...________ ________ J TEST POINT E WOR LINE LINE GROUP TERMINAL CONTROL MEMORY CORE PLANE WRITE CURRENT GENERATOR r 1 ___ I 4 112 I I I I L ________________E BOA _ _ _ ________ J END BOARD SELECTOR WRIT...

Page 256: ...1 ZlI ZlI LOWER CORES 0 Z 0 1 0 1 0 STORE l S z i C 1 0 I cnI N J I I 1 2 CLR 0 I 1_ r L 17 CORE PAIRS 17 CORE PAIRS I I NECESSARY CURRENT FLOW TO I MAGNETIZE CORES WHEN WRITING I t DIG iT CU T WRITE...

Page 257: ...sed the two stage sense amplifier provides a low signal which is gated by the strobe and sets the corresponding flip flop in the Zo register 3 WRITING Write operation is performed by passing the write...

Page 258: ...r performs the functions of the newly loaded routine which completes the transfer of all information and instructions for an operational program into the computer memory The operation of the bootstrap...

Page 259: ...SO REG ISTER S I REG ISTER ZO REGISTER 32 WORDS BOOTSTRAP PERMANENT MEMORY MEMORY CONTROL BOOTSTRAP MEMORY ADDRESS SELECTOR SI REGISTER READ 4 DIODE GROUP SELECTORS ORIGINAL CONT AND BOOTSTRAP MEMORY...

Page 260: ...hese positions provide signals that are gated by the strobe into the 20 register by setting the corresponding flip flops 4 3 POWER SUPPLIES AND POWER DISTRIBUTION a GENERAL Power for the computer logi...

Page 261: ...les f MISCELLANEOUS CIRCUITS 1 RUNNING TIME METER A running time meter Ml on figure 9 176 records total time that power is applied through relay Kl to the computer supplies 2 FAULT HORN The fault horn...

Page 262: ...G J t AI2S1 H J POWER SUPPLY INTERLOCK POWER S4 ON 1400 F f OFF 0 r F3 F2 FI F6 F5 F4 FI4 FI3 FI2 FI F2 F3 15V SUPPLY 4 5V SUPPLY 15 0 a 25 0V SU PPLY Figure 4 62 15 0 I 4 5 15 0 15 0 25 0 25 0 GRD T...

Page 263: ...3 3 time of instruction 71 the contents of the AL register are trans ferred to the arithmetic selector 1 I SEQUENCE I sequence table 4 12 is the first sequence performed during the execution of every...

Page 264: ...0 61 65 50 30 50 62 66 50 31 50 63 67 50 32 50 72 I Rl AND RIR2 SEQUENCES 70 50 33 50 73 71 50 34 50 74 20 73 50 35 21 77 50 36 22 50 01 50 37 23 50 02 50 50 I AND EXTENDED SEQUENCES I Rl AND EXTENDED...

Page 265: ...r W Clear HOLD 2 flip flop Clear PARITY flip flop Clear Select Stop flip flops Inhi bi t Con tro 1 Memory ZO Clear EF OD ACK GEN flip flop Clear F Register Clear MON and Special INT REG flip flops CON...

Page 266: ...Z Select Ari thmetic Selector Bits 00 17 Clear D Clear X Clear W Z Z Select T2 4 Arithmetic Selector D Z Select Bits 00 05 KO Z Select Bits 12 17 F Z Select Bits 06 11 F Clear Main Memory Enable flip...

Page 267: ...INHIBIT EAB flip flop Set INSERT EAB flip flop Set ALL INTERRUPT LOCKOUT flip flop Clear ALL INTERRUPT LOCKOUT flip flop Sample Selective Stops KOO K02 ICR KOO K02 SR Set INST FAULT flip flop Clear S...

Page 268: ...emory Protect Clear D Register Clear Zl Register Clear TERMINATE flip flop T4 4 CLR ACTIVE flip flop AL Ari thmetic Selec tor Ari thmetic Selec tor D Adder Zl Clear OVERFLOW flip flop Set TERMINATE fl...

Page 269: ...nd AU NEG T1 4 AL Ari thmetic Selec tor f f 02 03 06 07 14 17 20 23 R2 24 25 44 45 53 74 AU Ari thmetic Selec tor f 04 OS 06 07 26 27 46 47 Z Ari thmetic Selec tor f 56 Ari thmetic Selec tor X f f 24...

Page 270: ...tor X P 0 Set Inhibit EAB CLR AL CLR AU CLR P CLR Borrow Test flip flop Adder AL Adder AU Adder P Set Borrow Test flip flop CLR Zl Adder Zl CONDITICN f 24 27 and Y NEG f 02 03 06 07 16 17 22 23 53 56...

Page 271: ...Set Insert EAB If Borrow Test FF Set f 20 23 T3 1 T3 2 T3 3 T3 4 T4 1 CLR AU f 20 23 CLR Borrow Test flip flop f 20 23 T4 2 Adder AU f 20 23 Set Borrow Test flip flop If EAB f 20 23 T4 3 TABLE 4 15 WS...

Page 272: ...itiate Control Memory Sl P Zl ZO Inhibit Strobe Main and Control Memory Inhibit Strobe lower 6 bits ZO Zl Inhibit Strobe lower 12 bits ZO Zl CLR Insert EAB CLR SR Set INCREMENT P flip flop CLR X W CLR...

Page 273: ...Lower Rank Set I and Bl flip flops Memory Zl Adder P T2 3 CLR EAB flip flops Zl Z Select Z Selec t Ari thmetic Selec tor CLR 0 X W T2 4 Ari thmetic Selector 0 Ari thmetic Selector X Ari thmetic Selec...

Page 274: ...D T4 4 Adder Zl CLR Sl T1 1 P Sl I O Translator SO Enable Main Memory Initiate Control Memory Set INCREMENT P flip flop CLR ZO T1 2 Zl ZO Tl 3 Inhibit CLR F CLR D X W Zl Inhibi t Con trol Memory ZO Tl...

Page 275: ...r I Chan and Funct and Special Int Xlator CLR 20 1 3 2 F and K I O Trans lator 1 3 3 1 3 4 T4 1 Inhibit Clear Run I flip flop CLR 20 CLR Sequence Designator Upper Rank CLR 8 1 flip flop T4 2 Sequence...

Page 276: ...on time 4 usec I Rl 05 SELECTIVE SUBSTITUTE Execu tion time 4 usec I B modified Rl 06 COMPARE WITH MASK Execution time 4 usec I Rl 07 COMPARE WITH MASK Execu ti on time 4 usec I 8 modified Rl 10 ENTER...

Page 277: ...c I Rl RIR2 24 MULTIPLY AL Execution time 14 usec I RITl 3 Set A NEG FF if AL neg CLR 0 X WReg 4 AL Selec tor Selec tor 0 RIT2 1 Set MULT DIV SEQ OXLOl Set KO 1910 CLR AL if AL neg 2 CLR Kl Adder AL i...

Page 278: ...Rl Tl 2 3 4 AU Ari thmetic Selector Ari thmetic Selector X Arithmetic Selector X Ari thmetic Selec tor 0 CLR AU Set OXL05 CLR OXL03 Resume RI Sequence here Adder AU CLR HOLD I FF CLR 0 Set OXL06 CLR...

Page 279: ...Rl1 2 1 2 3 Set MULT DIV SEQ OXLOl Set KO 1810 CLR AU if AU neg CLR Kl Adder AU if AU neg CLR X CLR W CLR D first pass KO l Kl Set OXLOO Set Hold II FF on ly First pass and KO cf 0 HOLD I FF set and f...

Page 280: ...Signs Unlike Signs Unlike Signs Unli ke At this point this instruction enters I sequence of the next instruction to complete its operation CLR AL CLR OXL05 Adder AL CLR HOLD II FF Signs Unlike Signs U...

Page 281: ...ied ENTER B WITH CONSTANT I Execution time 4 usec Execution time 2 usec Execu tion time 2 usec Execution time 2 usec NOTE At this point this instruction enters I sequence of the next instruction to co...

Page 282: ...e Format II instructions following instruction 77 51 52 53 54 55 56 ORIGINAL SELECTIVE SET I RI SELECTIVE CLEAR I RI SELECTIVE COMPLEMENT I RI INDIRECT JUMP AND ENABLE INTERRUPTS I RI INDIRECT JUMP I...

Page 283: ...67 JUMP AL NEGATIVE I 70 ENTER AL WITH CONSTANT I 71 ADD CONSTANT TO AL I 72 STORE INDEX CONTROL REGISTER I 73 W B JUMP I Execution time 2 usec Execu ti on time 2 usec Execution time 2 usec Execution...

Page 284: ...ILLEGAL CODE I Execution time 4 usec Execution time 4 usec Execution time 4 usec EXecution time 2 usec FORMAT II INSTRUCTIONS Not Used SET INPUT ACTIVE Execution time 2 usec I SET OUTPUT ACTIVE Execu...

Page 285: ...equence of the next instruction to complete its operation I 50 14 ENABLE REAL TIME CLOCK MONITOR 50 15 TERMINATE INPUT I 50 16 TERMINATE OUTPUT I 50 17 TERMINATE EXTERNAL FUNCTION I 50 20 SET RESUME I...

Page 286: ...NAL INTERRUPT LOCKOUT I Not Used RIGHT SHIFT AU I T3 4 4 1 2 r 3 Set HOLD I FF Set OXL01 CLR K1 CLR X CLR W KO 1 K1 Set OXLOO Set Hold II FF 4 CLR KO Execution time Indeterminate Execution time 6 or 8...

Page 287: ...OO Set Hold II FF 4 CLR KO AURl X ALRl W 1 Kl KO CLR AL Set CLEAR HOLD FF Kl O 2 CLR Kl W AL L _ _ _ _ _ KO 0 KO 0 L _ _ 3 CLR OXLOO Set OXL02 KO l Kl CLR X CLR W 4 AURl X ALR1 W 1 CLR OXLOl 6 usee KO...

Page 288: ...LR X CLR W 4 AURl X ALRI W LOWER BIT OF AU UPPER BIT OF W 1 CLR OXLOI SCALE FACTOR I 1 3 1 1 3 4 Set CLEAR HOLD FF if shift count 0 Execution time 4 usee K 0 4 6 usee K 5 8 8 usee K 9 12 10 usee K 13...

Page 289: ...X W 4 AUL1 X ALLl W 1 CLR OXL01 Set CLEAR HOLD FF K1 0 and SCALE FACTOR FF was set or if shift count equals zero Complete I Sequence W LEFT SHIFT AU I Execution time 4 usec KO 0 4 T3 4 Set HOLD I FF...

Page 290: ...0 4 1 3 4 4 1 2 3 4 Set HOLD I FF Set OXLOI CLR Kl CLR X CLR W KO l Kl Set OXLOO Set Hold II FF CLR KO AULl X ALL1 W 6 usec KO 8 8 usec KO 9 12 10 usec KO 13 16 First pass and KO 0 First pass only UPP...

Page 291: ...e K 29 32 20 usee K 33 35 CLR X CLR W KO l Kl Set OXLOQ First pass and KO 0 4 CLR KO AULl X ALLl W UPPER BIT OF AL LOWER BIT OF X UPPER BIT OF AU LOWER BIT OF W 1 Kl KO 2 CLR AL CLR AU Set CLEAR HOLD...

Page 292: ...Execution time 2 usee I 50 56 STOP ON KEY SETTING Execution time 2 usee I 50 57 SKIP ON NO RESUME I 50 60 ROUND AU EXecution time 2 usee I 50 61 COMPLEMENT AL Execution time 2 usee I 50 62 COMPLEMENT...

Page 293: ...Paragraph 4 4c THEORY OF OPERATION 50 75 Not Used 50 76 Not Used 50 77 Not Used 4 150 CHANGE 2...

Page 294: ...n No circuit module repair procedures are included in this manual defective modules are replaced a INITIAL INSPECTION Following detection of a malfunction visually inspect the panel indicators switche...

Page 295: ...t easily isolated by use of the memory test program and by logical analysis Random memory errors may indicate improperly adjusted memory drive currents or read strobe timing NOTE Do not attempt to adj...

Page 296: ...ding the computer is important for two reasons to ensure the safety of operating and maintenance personnel and to maintain the dc level system used for I O communications The computer is grounded in t...

Page 297: ...PROCEDURES DATE extra weeks 1 2 Clean Air Filters Check System Ground Confidence Check Power Check Clean Cabinet Interior Wash and Oil Air Filters Check Memory Protect Record date and check off P M pr...

Page 298: ...raph 6 3j perform the following steps STEP 1 STEP 2 STEP 3 Vacuum filter Clean filter thoroughly in hot soapy water and dry with forced air Apply a thin coat of SAE u5 oil Wipe off excess oil with a c...

Page 299: ...THIS PAGE INTENTIONALLY LEFT BLANK...

Page 300: ...ce service and repair procedures A module extender figure 6 2 can be fabricated by connecting a 15 pin male module connector to a female connector with 36 inch lengths of wire b GENERAL PROCEDURES Gen...

Page 301: ...r 8130 132 No 14R2 The following bits and sleeves are used with item 10 Gardner Denver One 30 ga bit 501381 8130 143 One sleeve 17611 2 8130 129 One 30 ga bit 504221 8130 141 One sleeve 500350 8130 14...

Page 302: ...121 One sleeve 18840 8130 128 One 24 ga bit 26589 8130 120 One 24 30 ga sleeve 17611 2 8130 129 11 Unwrap Tool 30 ga Gardner Denver 8130 137 Unwraps wire wrap No 505244 connections 12 Unwrap Tool 20...

Page 303: ...CD fD 10 V If C I VARIABLE FORWARD PRESSURE Figure 6 2 Module Extender Schematic UNACCEPTABLE INSUFFICIENT FORWARD PRESSURE EXCESSIVE FORWARD PRESSURE Figure 6 3 Wire Wrap Connections If C I Q 0 0 tTl...

Page 304: ...AND REPAIR Figure 6 4 BIT SLEEVE A WIRE WRAP GUN WIRE __ __ L L _ TERMINAL POST B INSERTION OFWIRE INTO LONGITUDINAL GROOVE C POSITI ONING OF GUN WIRE AND TERMINAL POST Figure 6 4 Wire Wrap Gun CHANG...

Page 305: ...hed by twisting the handle 900 counter clockwise On some models a cap on the battery must first be unscrewed then the battery can be inserted into a conventional 117 vac 60 cycle electrical outlet for...

Page 306: ...es STEP 1 STEP 2 Swing open front panel paragraph 6 3a Use the combination tool to turn the exposed drawer locking screw figure 6 6 counterclockwise until the plugs on the rear of the drawer are disen...

Page 307: ...Figure 6 5 Figure 6 5 Drawer Front Panel SERVICE AND REPAIR PANEL LOCKING SCREWS 6 8 CHANGE 2...

Page 308: ...SERVICE AND REPAIR Figure 6 6 TEST BLOCK DRAWER TB2 LOCKING SCREW CLOCK SWITCHES TEST BLOCK SIS S2 TB2 Figure 6 6 Parts Location Panel Open CHANGE 2 6 9...

Page 309: ...Figure 6 7 DRAWER LOCKING SCREW DRAWER RETAINING SCREW SERVICE AND REPAIR SLIDE CATCH DRAWER RETAINING SCREW Figure 6 7 Chassis Fastener Location 6 10 CHANGE 2...

Page 310: ...be obtained by removing drawer A3 from the cabinet g VOLTAGE PROTECTION NETWORK LOCATION A voltage protection network is pro vided for the input voltages to each chassis These networks figure 6 6 may...

Page 311: ...Figure 6 8 SERVICE AND REPAIR Figure 6 8 Logic Chassis Open 6 12 CHANGE 2...

Page 312: ......

Page 313: ...Figure 6 10 Figure 6 10 Power Supply Extended SERVICE AND REPAIR LATCH FASTENERS 6 14 CHANGE 2...

Page 314: ...SERVICE AND REPAIR Fi gure 6 11 t 0 0 ell J 0 s l w a l a Z J J WW 0 1 0 0 a Z J 0 U 2 Z I W a I 0 l s 0 CHANGE 2 6 15...

Page 315: ...for this purpose Remove the necessary hold down strap or straps and slowly but firmly remove the module from the chassis jack Replace the module fasten the hold down straps and disengaging the upper...

Page 316: ...000 to to 067777 047777 01 02 Stack 7 Stack 5 Addresses Addresses 070000 050000 to to 077777 057777 El E2 DRAWER A3 CHASSIS 6 Figure 6 12 Memory Stack Location STEP 2 Open the chassis according to par...

Page 317: ...es usually Before attempting memory current adjustments ensure that failures intermittent conditions or marginal conditions do not exist in the computer logic and memory circuitry a COMPUTER SETTINGS...

Page 318: ...SERVICE AND REPAIR Figure 6 13 INHIBIT PULSE 820 MA READ PULSE WRITE PULSE 820 MA Figure 6 13 Memory Waveforms CHANGE 2 6 19...

Page 319: ...behind Stack 4 Set the currents and voltages in BANK 1 the same as for BANK 0 except use the 7500780 regulator card in location gJ30D To check the currents on chassis 5 follow the same procedure as f...

Page 320: ...race preamplifier at TP3 Strobe BANK 0 See figure 9 135 The pulse should be approximately 75 nanoseconds wide STEP 3 STEP 4 CHANGE 2 75 NS 3V o v Connect the Channel B probe to TP5 of the 7500650 card...

Page 321: ...bits and readjust the strobe timing as above c TESTING MEMORY Perform the diagnostic memory test after the memory strobe adjustments have been made If an error occurs in the normal high or low margins...

Page 322: ...the following settings VOLTAGE REGULATED SUPPLY Measure the voltage at TB2 C33 on chassis 8 figure 9 134 Using the pot marked located on the chassis next to the test points adjust for 16 vdc o VOLTAGE...

Page 323: ...IOYOI 020YOI C w C t a z w w 63C24 EVEN CLOCK J 0 a a a 0 z 03DYOI SERVICE AND REPAIR TBIC33 0 a a z C w C t a o 8 63CI3 000 CLOCK J a 0 z TAP POSITIONS SHOWN ARE NOT NECESSARILY AS CONNECTED IN THE C...

Page 324: ...the readout for the weakest pulse STEP 9 Load and run the FACT Control Memory test to insure that a recheck and or readjustment of the timing is not necessary STEP 10 With the FACT Control Memory test...

Page 325: ...moving the chassis The upper wire TP l is for checking the read current and the upper pot is the adjustment While observing the memory currents if you vary the pots from one limit to the other the rea...

Page 326: ...again STEP 8 Adjust the variac to about 110 volts then master clear the computer STEP 9 Reduce the variac until the computer voltage fault indicator lights This is the voltage fault voltage STEP 10 R...

Page 327: ...has just gone negative and then back it off so that it is just positive againo Repeat steps 1 thru 3 for chassis A3Al if the computer has more than 32K of memory Remove the variac and reconnect the 40...

Page 328: ...embly e DESCRIPTION This column lists the item name of a part or assembly followed by an identifying description Whenever parts are procured from a vendor e the vendor s part number is listed in the P...

Page 329: ...nal Connector Corp 9210 Science Center Minneapolis Minn 55429 Singer Co The Diehl Division Finderne Plant Finderne Ave Somerville N J 08876 Code 37942 43766 56289 71468 71744 72619 75382 80023 80183 8...

Page 330: ...eral Systems Division Univac Park P O Box 3525 St Paul Minn 55101 Augat Inc 33 Perry Ave Attleboro Mass 02703 Code 91637 91885 91886 91929 95267 96881 96906 Name and Address Dale Electronics Inc P O B...

Page 331: ...17 I T I 26 29 5 IllVl 1I1 14 8 ____ I I IIII JlI 2 I I II 15 7 1 II IV III 1111 11 4 9 18 __ III I I II II I 16 3 __ 11I 11 II I 34 111I1 1 12 10 33 19 20 6 21 25 Figure 7 1 Digital Data Computer fr...

Page 332: ...36 7049747 0Q REF J A COt PUTI t UIGITAL DATA 90536 7049747 10 RE F K A COI lpuTI R UIbITAL DATA 90536 7049747 11 REF L B ACI E lSORY INTEGHAL I O AND 90536 7051213 00 1 A D II MuRY I B ACI E SORY INT...

Page 333: ...C MEMORY DRAwER ASSEMBLY IFUR 90536 7053750 03 1 a c BHE KUOWN SEE FIG 7 31 A3 C MEMOKY DRAWER ASSEMBLY IFOR 90536 7053750 04 1 L BREAKDOWN SEE FIG 7 31 4 A4 C CONVt RTER DIGITAL TO DI61TAL 90536 705...

Page 334: ...ML GrI J L C WA Ht R FLAT 0 25 IN xu IAPI 96906 MS15795 810 4 A D G I J L 13 C HOOD AbINET 90536 7050305 00 1 A D G I J L C SCHEw PAN HO 6 32UNC 2A BY 4912524 13 4 A D 1 70 IN G IAPI COML GrI J L C SC...

Page 335: ...HU 0 312 181INC 2A BY 4912530 00 2 A D 0 5 IN Lb lAP FOR INlJEXt S 15 COML GrI AND 101 J L D eKEw FLAT HD o 0312 24UNF 2A 908542 05 2 A D BY U 87t IN LG lAP FOR INDEXES COML G I It AND 161 J L 0 SCKE...

Page 336: ...00 8 17 AND 181 C S CkEw PAN HD 0 312 18UN 2A BY 912530 00 A 0 5 IN Lu lAP FOR INDEXEs 17 COML AI lO ltV C SCREW FLAT HD 0 312 2 UNF 2A 9085 2 05 8 BY U a75 IN LG lAP FOR NDEXES COML 17 ANU IBI C SCI...

Page 337: ...521 04 6 0 1 IN L G IAPI COML C WASHt R FLAT NO 10 IAPI 96906 MS15195 808 6 22 C ADApIER CABLE TO CONNECTOR 96906 MS3051 12R 1 3 C GA Kt T LAT SQUARE 901211 01 1 82801 04 0402 0020 24 C COI lNt CTOI P...

Page 338: ...BUARD 131349 8T86 1 l D It J L 32 C STABJ LIZER ASSEMBLY IFOR BREAK 90536 7050267 00 1 A D DOWN SEE FIG 7 01 6 1 C STABJ LIZER ASSEM LY FOR BREAK 90536 7050265 00 1 B C DUW E FIG 7 21 E F C TABJ LIZE...

Page 339: ...Figure 7 2 PARTS LIST 8 l 8 9 r r rrTI I rV G 2 P2 Ina F V 3 E V V V r lJ qE j 4 o f r po r 5 tJD c 6 PI B nl A L L Figure 7 2 Digital to Digital Converter Al A2 A4 A8 Sheet 1 of 7 7 12 CHANGE 2...

Page 340: ...20 4 2 8 24 9 4 25 9 25 19 19 19 19 19 19 0 14 14 14 14 14 14 24 24 5 5 5 6 2 25 24 8 8 9 5 7 9 25 5 5 18 18 18 18 18 18 18 18 18 8 0 11 11 11 11 11 11 11 11 11 28 28 28 9 5 c 5 6 6 6 18 18 18 18 18 1...

Page 341: ...20 20 20 20 4 2 8 24 9 4 25 9 25 14 14 14 14 14 14 c 19 19 19 19 19 19 24 24 5 5 5 6 2 25 24 8 8 9 5 7 9 25 5 5 8 11 11 11 11 11 11 11 11 11 28 28 26 28 28 18 18 18 18 18 18 18 18 18 9 o C 5 5 11 11 1...

Page 342: ...5 8 6 8 25 25 4 8 25 24 2 26 26 8 5 9 8 9 8 2 2 24 2 8 8 24 9 24 4 2 2 2 2 I I 7 25 9 8 25 25 8 6 2 4 24 9 26 26 9 8 9 2 2 8 2 8 24 2 8 2 24 2 24 7 2 4 4 32 8 9 8 25 9 25 10 8 4 9 4 26 26 7 8 8 8 8 8...

Page 343: ...45 24 25 25 6 6 6 6 6 6 9 5 7 3 3 3 3 3 3 25 25 25 25 25 7 25 25 24 24 24 5 24 24 24 5 2 2 2 2 2 2 2 2 9 9 9 9 2 2 2 2 2 2 7 7 7 7 7 7 7 7 2 2 2 8 2 2 2 5 24 8 8 6 6 6 6 6 6 9 5 7 3 3 3 3 3 3 25 9 25...

Page 344: ...3 2 3 3 3 7 3 8 9 8 25 9 26 4 4 8 26 4 4 8 8 9 8 9 7 23 27 2 2 2 2 2 2 8 2 2 2 2 2 2 8 8 2 2 2 2 8 26 2 2 2 2 5 4 2 12 12 12 27 5 9 4 4 3 3 3 2 3 3 3 7 3 2 9 24 5 8 3 3 8 9 4 4 24 24 16 8 4 4 4 6 27 8...

Page 345: ...__ J 7 7 7 26 9 7 24 5 6 8 25 25 7 3 3 3 3 3 43 39 43 39 47 2 2 8 26 17 2 2 2 6 25 2 7 7 2 2 2 2 2 22 30 38 34 34 35 35 34 34 35 35 42 42 42 42 42 7 29 29 7 7 24 24 6 7 25 7 7 3 2 3 3 3 41 41 31 31 31...

Page 346: ...FOR REAKOOWN SEE FJ G 7 81 A1 0 CHAS IS ASSEMBLY ELECTRI AL 90536 7053194 02 1 C E UIPMENT IFOR BREAKDOWN SEE FiG 7 81 A1 D CHASSIS ASSEMBLY ELECTRICAL 90536 1053194 04 1 0 EQUiPMENT IFOR REAKDOWN SEE...

Page 347: ...00149 00 2 lI CRb 91506 803A 1G3 11 D OS XL LATOR PULSE DELAY 90536 1000210 00 3 8 0 OSl L LATOR PULSE DELAY 90536 1000210 0 1 1 C 12 D AMPUFIER DRIVER 90536 1002013 00 32 A D E D AMPUFIEf DRIVER 9053...

Page 348: ...6 7002060 00 19 B F 19 0 INVEKTER 1 1 1 1 1 90536 7002070 00 29 A E D INIIEKTER 1 1 1 1 1 90536 7002070 00 43 C D INIIEKTER 1 1 1 1 1 90536 7002070 00 24 D D INIIEI TER 1 1 1 1 1 90536 7002070 00 14 B...

Page 349: ...0 00 54 A E D FUP FLOP 2 221CI 90536 7002900 00 56 C U FUP FLOP 21221CI 90536 7002900 00 19 0 D FL 1P FI OP 2 221 1 90536 7002900 00 17 B F 35 0 INIIEt T R AND OR 334 90536 7002920 00 8 A E 0 INIIEt T...

Page 350: ...90536 7003680 00 4 0 46 0 NETWURK PULSE DELAY 1200 NSECI 90536 7003710 00 2 0 47 0 SENsuR VO TAGE l l 5 VOLTI 90536 7003720 00 1 0 48 0 AMI LIFIEI I REGULATOR IP10 VOLTI 90536 7003730 00 1 0 49 0 AMPl...

Page 351: ...I N t n c rr I N 3 111 35 18 8 81 o 7ii 01 a 011111111 I1I1I111 c I N o 121 ASSY 7053750 Ie e eJ re s 14 r o o Figure 7 3 Memory Assembly A3 Sheet 1 of 3 N 2 Y l to s I W 0 0 j en r H...

Page 352: ...l c t z G l t l 1 1 J I I c n 15 A 7 u 3 6 Figure 7 3 Memory Assembly A3 Sheet 2 of 3 16 17 JIJ ro SECTION A A 9 THRU 14 0 t 0 t 3 Ul r H Ul t 3 r J to I ell J I W...

Page 353: ...6 26 26 26 26 26 6 26 26 6 26 26 26 26 31 28 8 27 25 25 25 29 25 25 7 28 28 10 11 12 13 14 15 16 17 18 32 3C 30 O 30 3C 30 22 2 21 1 38 38 28 8 7 25 2 25 9 25 25 25 27 8 28 31 6 26 26 126 26 26 6 26...

Page 354: ...IFOR tlREAKOOWN SEt FlG 7 181 3 0 IJOUR ASSEMuLY 90536 7085701 00 1 4 E LATCH RIM CLINCHING 90536 7008890 00 1 5 E SPACt R 5LI F VE 90536 7033086 00 1 b E STUD TURNLOCK FASTENEK 90536 7025359 00 2 E R...

Page 355: ...IER nRlvER 90536 1500040 00 3 A D AMPLJ FIER DRIVER 90536 1500040 00 2 B D D AMPLJ FIER nRIVEri 90536 1500040 00 6 C 22 0 OSCIL LATOR CLOCK 90536 1500260 00 1 A B D D OS IL LATOR CLoCK 90536 1500260 0...

Page 356: ...ER LEVEL CHANGE 90536 7500761 00 6 A B D D AMI UFIEH LEVEL CHANG 90536 7500761 00 12 C 31 0 CAI A lTOR UIODE ASSEMBLY 90536 7500660 00 4 A 0 CAI A ITOR UIODE ASSEMBLY 90536 7500660 00 2 B D 0 CAPA lTO...

Page 357: ...rr I N R9 R7 R R3 RI I r L51 51 XD51 I I p q C Of _N C3 CI 0 XD52 J R8 R6 R4 R2 C2 0 52 XD53 53 XD54 XD55 XD56 14710 121518Ih l 1 4 3 OQ Figure 7 4 Hood Assembly AS XD57 54 U Q mG 9 MI 0 T 1 cO s oj 1...

Page 358: ...S17325 1 1 kl 0 RE I TOR 81349 RC07GF471J 5 THRU R4 R5 0 RESI TOR 81349 RC20GF150J 1 THRU R9 SI 0 S lWJ Tl H 96906 MS35059 21 1 S2 0 SW lT H 96906 MS25068 23 1 S3 D SWJ Tl H TObGLE 2 SPOT CONT ACT 790...

Page 359: ...8 J9 JIO JII JI2 JI3 JI4 DDDDDDDD TOP VIEW OF CABINET JI7 r F I N THRU F6 XFI THRU XF6 J3 J2 o A2 J3 J2 AI FI THRU F6 XFI THRU XF6 I I r J4 JI W JI J W4 A4 W3 W2 Q FI THRU F6 JI XFI THRU o XF6 B Figur...

Page 360: ...CTOH RECEPTACLE EL C 7900842 00 4 THRU n I AL MALE 169 CONTACTS 91886 3614875 AlJ4 AIXFl C FU EHOLDER 81349 FNH26G2 6 THRU A1XF6 A2 0 CONNt CTOH SUBASSEMBLY 90536 701Q245 02 1 ELE THICAL A2F1 C FU E...

Page 361: ...885 3614875 A4 J4 WIRt WRAP A4W1 0 BU AR Gt OUNO 90536 7050281 00 4 THRU A4W4 A4XF1 C FU EHOLDER 81 549 FHN26G 6 THRU A4XF6 Jl C CONNt CTOR RECEPTACLE ELI C 906489 00 17 THRU THI AL MALE 90 CONTACT 71...

Page 362: ...PARTS LIST CHANGE 2 FI THRU F6 XFI THRU XF6 Figure 7 6 ODD 000 000 DDJD o _____ AI JI W5GND Figure 7 6 Connector Assembly A13 7 35...

Page 363: ...BLY 90536 7019245 02 1 ELEI TRICAL AIFl C FUSE 81349 F02A250V5AS 2 AIF4 AIF2 C FUSE 81349 F02A250V12AS 2 AIF5 A1F3 C FUSE 81349 F02A250V4AS 2 UFb A1 J1 0 COI Nt CTOR RECEPTACLE EL C 7900842 00 THRU H...

Page 364: ...PARTS LIST Figure 7 7 2 4 6 I 2 1 3 ru __ LQ d Figure 7 7 Filter AssemblYt Radio Interference A14 CHANGE 2 7 37...

Page 365: ...FL3 2 PI D CONNt CTOH 96906 MS3100A20 15P 1 3 0 BOX ELECTkICAL FILTER 90536 7033255 00 1 It 0 CONDUIT ASSEMBLY METAL 7900912 13 1 FI EXIBLE 01021 C175 0500 5800 A2q9 5 D DUMMY CONN CTOR SHELL ROUND 90...

Page 366: ...I I I I I 2 VIEW A A 6 c I 18 F I I VIEW B B b L 89 8 r n t1 f s I I s c 7 0 0 o 0 0 I I I I I I 9 0 I 0 ___ 0 0 0 f I I b 0 1 i 0 ___0 4 0 0 F 0 0 I I I I I 9 9 c c 9 I I I I I I 0 __ 0 0 0 It J Fig...

Page 367: ...E CONN CTOH ASSEMBLY ElECT ICAL 90536 701Q232 00 1 2 JlA F CONN CTOR RECEPTACLE EL CTHI 7900251 01 2 5 THHU CAL fEMALE 15 CONTACT 16512 A2345 10 J3 A J1B THRU J35b J1C THRU J35C JlD THRU J350 J1E THR...

Page 368: ...PARTS LIST Figure 7 9 13 2 9 I I II 12 7 VIEW A A u 10 0 0 0 VIEW B B 0 II A 6 3 A 5 B N on I 4 I I 0 I I l 0 B 3 7 Figure 7 9 Connector Assembly A4A2 CHANGE 2 7 41...

Page 369: ...00 2 A1J42 4 A1A3 F CA A ITOR RESISTOR 90536 7024791 00 1 5 A3Cl F CA A ITOR 81349 CL25BG251UP3 4 THRU A3C4 6 A3Rl F RESI TOR 81349 RE65N43R2 2 A3R2 7 E RETAINER ELEXTRONIC CIRCUIT 90536 7019281 00 4...

Page 370: ...J r t t 1 N J I t W CIG CIA C7 c l II Figure 7 10 Resistor Assembly A4A2A2 C5 C3 CI t I t c H r fl r H TJ co s J I o...

Page 371: ...C16 tI P8U Ql E TRAN ISTOR 813 9 2N539 1 RI E RE I TOR 813 9 RE65N 6R 36 THRU R3a R31 E RE I TOR 813 9 RA30LASB100A 2 R38 R39 E RESI TOR 813 9 RE6 N40R2 4 THRU R 2 R 3 E RE I TOR 813 9 RC01GF391J 2 R...

Page 372: ...PARTS LIST Figure 7 11 9 SECTION A A 3 4 3 B B L 1 SECTION B B j C 6 r A A I C 7 8 2 VIEW C C Figure 7 11 Electrical Equipment Door Panel Assembly A3 CHANGE 2 7 45...

Page 373: ...OWN SEE FIG 1 121 2 E DOOR ELECTRICAL EQUIPMENT 90536 1033949 00 1 B CABINET E DOOR ELECTRICAL EQUIPMENT 90536 7033949 01 1 A C CABINET 3 E LATCH RIM CLINCHING 90536 1008890 00 1 4 E PAWL 1 68 IN LG 9...

Page 374: ...EX DESCRIPTION PER 00 NO DESIG CODE MFR PART NO ASSY CODE 11 E TAY FOLDING 90536 1019296 00 1 B U 428 I l LG IAPI E SCkEw MACH FLAT HD 0 3C UNC 2A Q6906 MS51959 201 2 E WA H R FLAT NO b IAPI Q 90 MS31...

Page 375: ...Figure 7 12 7 48 4 H 7 3 t t tt 2 1JJ _ 7 Figure 7 12 Control Indicator Assembly AIA3 PARTS LIST CHANGE 2...

Page 376: ...WITCH 96906 MS25086 23 B THRU 58 2 59 F SWIT H 813 9 SRO B36C3MPC2 4N 4 THRU 512 3 XOS2A F SWITCH PUSH INDICATOR TYPE 7900 96 23 126 XOS4A WITH LAMP TRANSISTORIZEU 72619 908 1166 1633 THRU 526 XOS12A...

Page 377: ...Figure 7 13 PARTS LIST ft t O t o O t O t t O 7 0 2 0 t O t 2 3 5 6 4 Figure 7 13 Control Indicator 7 50 CHANGE 2...

Page 378: ...10 POSHION 91929 13AT418T2 3 511 F SWlTl H TOGGLE 2 POLE 1900635 02 1 POSHION 91929 13AT416T2 4 S12 F SW Tl H 96906 MS35059 23 4 THRU l15 5 Hl F RE lI ITOR 81349 RV4NYSDI05A 1 6 F KNOB 96906 MS91528 1...

Page 379: ...EF MFR UNIVAC PART NO USE INDEX DESIG DESCRIPTION CODE PER a J NO MFR PART NO ASSY CODE 13 THRU XOS14C XOS1H THRU XOS10t XOS12t XOS13t XOS14t XOS11 THRU XOS51 XOS81 XOS91 XOSll I XOS13I XOS141 XOS1 J...

Page 380: ...PARTS LIST Figure 7 14 10 9 SECTION A A 5 4 8 8 L 6 SECTION 8 8 I C r A A f C 8 2 7 VIEW C C Figure 7 14 Door Panel Assembly A3 CHANGE 2 7 53...

Page 381: ...Lt EVE 90536 7019290 00 1 6 E STUD TURNLOCK FASTENER 90536 7025360 00 1 E RING RETAINING TURNLOCK FAST 7900836 00 1 ENEK IAPI 0852 DI02lAi E SPHING HELICAL COMPRESSiON 90536 7025366 00 1 IApl 7 E HING...

Page 382: ...PARTS LIST Figure 7 15 5 J 000 000 000 2 000 4 000 T 2 000 4 00 2 L _ _ _ _ Figure 7 15 Control Indicator Assembly A4A3 CHANGE 2 7 55...

Page 383: ...TON 100 MA 07137 MBS S1838A9 Sl 3 110 VAC S16 3 XOS7A F SW T H PU H INOICATOR TYPE 7900496 23 84 XOS18 WITH LAMP TRANSISTORIZEU 72619 908 1166 1633 THRU 526 XOS7B XOSIC THRU XOS8C XOSllC XOS2U lHRU XO...

Page 384: ...32 29 19 23 22 33 2 22 15 _ _ 14 VIEW A A ROTATED 90 CCW 17 gL 2 __ IJ JL 37 46 38 39 30 11 28 12 27 f 21 VIEW B B ROTATED ISOo Figure 7 16 Power Supply PSI Fig ure 7 16 2 17 36 5 40 4 45 31 l1H 18 C...

Page 385: ...CE DIouE 81349 IN1186 18 THRU CR18 5 CR9 C SEMICONDUCTOR DEVICE DIOUE 81349 IN1202 12 THRU CR24 CR27 THRU CR32 6 CR25 C SEf 1I ONDUCTOR DEVICe DIODE 81349 IN2807B 1 7 CR26 C SEMI ONDUCTOR DEVICE DIODE...

Page 386: ...TRAN FORMEK POWE R 5TE P UOWN 4913127 00 1 pRIMARY 115 V 400 HZ O PHASE 80023 53802B DtL1A TO 3 PHASE DOUBLE wYE stCVNQARY 24 3 v AT 23 AMp 24 T2 C TRAN FORMEH POWER STE P UOWN 4913126 00 1 PHI ARY 11...

Page 387: ...j7 C SUOt TEL SCOPING 22 IN Lb 7901056 01 1 05236 350266 R 38 C 5h M TELE5COPIN6 SLIDE 90536 7025682 00 3 C SCHEtI FLAT HO 10 32UNF 2A 4912507 03 4 B U 625 IN LG lAP FOR INDt XES COML 41 NU 421 39 C L...

Page 388: ...PARTS LIST Figure 7 17 L ___ _ O o 53 52 BI l CI Jl l I I I I I I I I 0 I I iQj TBI 0 a a o 0 Figure 7 17 Fan Assembly A6 CHANGE 2 7 61...

Page 389: ...F504K 1 C SCKEw MAChINE PAN HD 4912524 04 6 32 UNC 2A 0 5 IN LG IAPI COML S2 C SWIT H TH RM05TATIC SPST 4912495 10 5 ALED CONTACT5 CLOSE ON T MP 82647 4286A2 184 1 It CI EASE 111 DEG F 144 UEG CI TO 1...

Page 390: ...1 I 82 I I H s l m _ _ I 21 21 w f If Oi I 02_ J r I L Jti o 01 I m ___ o em u rom 0 f O I E2 j 1 40 _ l __ 20 II 0 o o A o 8 o o o 36 15 14 25 13 3 25 9 12 25 10 1 r l 25 II liCIL25 10 25 33 I 142 38...

Page 391: ...Figure 7 18 PARTS LIST o CD I CD N H I4J 0 N 0 0 a a c f 0 0 N c t i Q S 17 8 7 6 a 4 en en c t en 1 en en ro c u 9 18 24 s a 5 Q 1 0 W i ro U 1 U a i W I a I i I I a 0 1 19 4 7 64 CHANGE 2...

Page 392: ...3 9 CL25BH301UP3 1 THRU C9 5 CHI E SEMI ONDUCTOR DEVICE DIOUE 813 9 IN1202 A THRU CR8 b eR9 E SEMICONDUCToR DEVICE alOUE 813 9 IN2A06B 1 1 CRI0 E SEMI ONDUCToR DEVICE OIOUE 813 9 IN2AO 8 1 8 CRll E SE...

Page 393: ...91506 8038 1G3 XCRU XQl 25 XFl E FUSEHOLDER 813 9 FHN26G2 9 THRU XF9 26 E GU1D CARD 90536 7053763 00 1 27 E GUIDI CARD 90536 705376 OO 2 28 E GUID CARU 90536 7053765 00 1 29 E 6U1Dt CARO 90536 705376...

Page 394: ...IPTION PER ON NO DESIG CODE MFR PART NO ASSY CODE Id l E CLAMP LOOP NYLON P STYLE 900129 03 2 09922 HP N 2 E CLAMP LOOP NYLON P STYLE 900129 05 1 09922 HP6N 3 E FRAMt CHASSIS f LECTRICAL 90536 7053753...

Page 395: ...Figure 7 19 4 67 I weB A I ____ AJo r r L J I F U c r J o____o J W9 19 AIF WI o 0 r J i J 0 1 I j WII _ __0 5 4 Figure 7 19 Electrical Connector Panel Assembly AI PARTS LIST 2 7 68 CHANGE 2...

Page 396: ...CONN CTOR RECEPTACLE ELEC 7902239 01 1 T I AL MALE WIRE WRAP 120 91886 5593566 CONTACTS 2 1 F BU AR GROUND 90536 7078035 04 8 THRU W5 8 THRU wll 3 W6 F BU bA R GHOUNO 90536 7078035 05 2 7 1 F GROMMET...

Page 397: ...J J J 0 n c t Z N 4 QI Q5 2 3 2 3 Figure 7 20 Electrical Component Assembly A2 and A3 Q7 2 7j c Q s t j 1 J J I 0 0 P tJ 3 Vl r H Vl 3...

Page 398: ...1 4 NUN INDUCTIVE 7 5 OHM PORM 1 91637 NH10 7 5 1PCT R7 LO W 3 R2 F RE I TOR FIXEU WIRE wOUNU 7900497 17 4 R3 NIJN INDUCIIVE 15 OHM pORM 1 91637 NH10 15 0 1PCT R5 J O W R6 F SCkEii MACHINE PAN HD 2 56...

Page 399: ...Figure 7 21 PARTS LIST 4 r t 0 0 0 0 0 0 0 0 0 0 0 o 0 0 I J 0 I 3 2 Figure 7 21 Stabilizer Assembly 7 72 CHANGE 2...

Page 400: ...ATE 903090 16 2 5IE L 3 8 16UNC 2A 2 IN LG COML C wA5H R LOCK SP ING 0 375 IN 96906 MS35332 141 2 IApl IU IAPI C NUl PLAIN HEX FINISHED 96906 MS51971 3 2 0 3 5 1bUNC 2f j IAPI 2 C Nul Tt IP 90536 7045...

Page 401: ...Figure 7 22 PARTS LIST A l I 0 0 0 0 2 r V l 0 3 0 0 0 L I I Figure 7 22 Stabilizer Assembly 7 74 CHANGE 2...

Page 402: ...EX HD CAU pLATE 903090 16 2 srEc L j 16UNC 2A 2 IN LG COML IApl C WASHc R LOCK SPkING 0 3 l 5 IN 96906 MS35338 141 2 IU IAPI C NUl PLAIN HEx FINISHED c 6906 4912541 02 2 0 3 5 16UNC 2H IAPI 2 C NUl Tt...

Page 403: ...0 MS3108BI0SL35 5 F03A125v20AS 16 11 MS3108820 15S 1 24 F03A12SV20AS 18 11 MS31S795 805 11 F03A250Vl0AS 5 MS35059 21 4 F03A250V12AS 4 M5350S9 23 13 4 F03A250V12AS 5 MS35059 23 15 1 F03A250V12AS 16 13...

Page 404: ...20 00 2 35 7002930_00 2 36 7003180 00 2 37 7003480 00 2 38 700 490 00 2 39 7003600 00 2 40 7003621 00 2 IH 7003630 00 2 42 7003640 00 2 43 7003670 00 2 44 7003680 00 2 45 7003710 00 2 46 7003720 00 2...

Page 405: ...47 02 1 705 5783 02 12 7085707 00 3 14 7049747 03 1 7053783 03 11 1 7085708 00 3 12 7049747 04 1 7053783 03 12 7500040 00 3 21 7049747 05 1 7053785 00 1 7500260_00 3 22 7049747 06 1 705 5785 01 1 7500...

Page 406: ...1 7900836 00 h 7QOOB41 no 8 4 7900841 00 9 12 790n842 00 5 7900842 00 6 7900843 00 8 3 7Qon843 00 9 11 790n87 oo 4 79an8BO oo 12 4 7900880 00 15 4 7900906 01 3 7900906 01 3 11 7900912 13 7 4 790n9 7 0...

Page 407: ...THIS PAGE INTENTIONALLY LEFT BLANK...

Page 408: ...input inverting amplifier It operates with nominal static vOltages of 0 0 volts and 4 5 volts The cir cuit provides a low output for a high input and a high output for a low input The inverter is repr...

Page 409: ...WO LOWS IN TO AND I HIGH OUT ALL LOWS TO AND 2 HIGH OUT ONE OR MORE HIGH TO BOTH AND s LOW OUT c AN OR INvERTER TYPICAL SYMBOLOGY I OUTPUT 2 TO 8 INPUTS ALL LOWS IN HIGH OUT ANY HIGH IN LOW OUT b AND...

Page 410: ...CLEAR INPUTS SET INPUTS a FLIP FLOP TYPE 2020 0 SIDE i I SIDE 0 OUTPUT LiNE FLAGGED FOR II SET CONDITIONS I OUTPUT LINE 0 OUTPUT LINE I OUTPUT LINE E FLAGGED FOR SET L CONDITIONS 0 SIDE CLEAR INPUT I...

Page 411: ...ER iII P TYPE 2330 OUTPUT AMPLIFIER TYPE 2130 LINE DRIVER SYMBOLOGY P TYPE 2090 AND 2320 INPUT AMPLIFIER _ P TYPE 2340 OUTPUT AMPLIFIER TYPE 2140 LINE DRIVER TYPE 2100 INDICATOR DRIVER Figure 8 3 Typi...

Page 412: ...ver circuits are assigned a unique logic notation to identify the cycle and phase of the signal being transmitted The amplifier driver is represented symbolically as shown in figure 8 3 Three common o...

Page 413: ...derived from the following alpha assignment list A Arithmetic Register Accumulator and Adder B BU Register C Input Output Communications Registers D Arithmetic Register E Control F Function Register...

Page 414: ...HOW SET CONDITION DESIGNATION 0 SIDE OF r IXZOI FF 2000 FLIP FLOP 7J7G C 10 OUTPUT PINS I SIDE OF FLIP FLOP CARD TYPE LOW FLAG INDICATES LOW VOLTAGE REQUIRED TO ACTIVATE CIRCUIT ir liI ___ 1 NPUT PI N...

Page 415: ...the lo cation of a card in the computer by chassis number and chassis coordinates As shown below the first digit in the designator identifies the chassis number For duplicate circui ts the chassis nu...

Page 416: ...HASSIS 6 AlAI AI I I I I I AIA2 I A3 I I I I A3AI A3A2 ID A5 I I I I I I I A2 A2AI I A2A2 PSI ID Figure 8 5 AIO CHASSIS 4 HASSIS 9 A8 yCHASStS to CHASSIS 3 A8AI I A8A2 CHASSIS 8 CHASSIS 7 Figure 8 5 D...

Page 417: ...elements are identified by signal names or special symbology to name the signal transmitted and or to define a logical event In addition to the signal or special symbol that appears above the signal...

Page 418: ...ED IOT21 IS FOUND 9 REFERS TO SECT ON 9 UNIQUE DESIGNATOR OF SOURCE CIRCUIT II o N OUTPUT LINE INPUT LINE 0 W I j E j fl z Figure 8 6 OUTPUT SIGNAL NAME READS A LOW IMPLIES THAT THE X REGISTER IS ENAB...

Page 419: ...NE P JACK 6 ON CHASSIS 2 PLUG P2 ON 9 19 CHASSIS 2 PINS 9 AND 19 foII P CABLE JACK J3 ON CHASSIS 7 CABLE JACK J ON CHASSIS 3 7P3 1 SYMBOLOGY PLUG P3 ON CHASSIS 7 PIN 1 t INTER CHASS IS ___ CABLE PLUG...

Page 420: ...ircuits and terminates in a 56 pin connector The type B cards are used in memory logic and control to minimize space and provide maximum memory storage capability Card type numbers listed in the funct...

Page 421: ...ptions 1 Card name and card type number 2 Symbol used to represent the card on the functional schematics 3 A logic description and a design description when applicable b TYPE B PRINTED CIRCUIT MODULES...

Page 422: ...02 0 t 02510 6 0 51 O 6 035 09 6 03511 8 1 1 1 1 1 2 07 0 1 Figure 8 8 Sample Chassis Map Figure 8 8 1XJ 07 1XJ 09 1XJ 06 1XJ 08 G FF FF 293 0 293 0 DO F NOT U5E 91Y1 O 98Y10 3 3 9 OY03 3 A IA LSO 209...

Page 423: ...per second The amplitude of the output signal is from 0 0 volts to 15 0 volts This circuit is used to supply sub stitute timing pulses for maintenance and test purposes LOGIC INPUT OUTPUT HIGH 0 0 Vo...

Page 424: ...lts HIGH 0 0 Volts LOW 4 5 Volts LOW 4 5 Volts ELECTRICAL DESCRIPTION Input signals to this circuit must have nominal positive voltage excur sions of 0 3 volt and nominal neg ative voltage excursions...

Page 425: ...ominal nega tive voltage excursions of 4 5 volts The output voltage levels are identi cal to the input voltage levels The maximum input current required is 5 8 milliamperes with 0 0 volts in put This...

Page 426: ...CTRICAL DESCRIPTION Input signals to this circuit must have nominal positive voltage excur sions of 0 0 v lts and nominal neg ative voltage excursions of 4 5 volts The output voltage levels are iden t...

Page 427: ...st have nominal positive voltage excur sions of 0 0 volts and nominal neg ative voltage excursions of 4 5 volts The output voltage levels are identical to the input voltage levels This logic element i...

Page 428: ...CRIPTION Input signals to this circuit must have nominal positive voltage excur sions of 0 0 volts and nominal neg ative voltage excursions of 4 5 volts The output voltage levels are identical to the...

Page 429: ...gure 8 15 Inverter 8 22 ELECTRICAL DESCRIPTION Input signals to this circuit must have nominal positive voltage excur sions of 0 0 volts and nominal neg ative voltage excursions of 4 5 volts The outpu...

Page 430: ...d nominal neg ative voltage excursions of 4 5 volts The output voltage levels are identical to the input voltage levels The maximum input current required is 5 8 milliamperes with 0 0 volts input The...

Page 431: ...ositive voltage excur sions of 0 0 volts and nominal neg ative voltage excursions of 4 5 volts The output voltage levels are identi cal to the input vOltage levels The maximum input current required i...

Page 432: ...ION Input signals to this circuit must have nominal positive voltage excur sions of 0 0 volts and nominal neg ative voltage excursions of 4 5 volts The output voltage levels are identical to the input...

Page 433: ...to a level between 0 0 and 0 5 volts and negative volt age excursions between 13 5 and 16 5 volts Input signals are applied to either pin 12 or 14 The gating signals applied to either pin 5 or 6 have...

Page 434: ...Volts HIGH 0 0 volts LOW 4 5 Volts LOW 15 0 volts ELECTRICAL DESCRIPTION Input signals to these elements must have positive voltage excursions be tween 0 0 and 0 5 volts and negative voltage excursion...

Page 435: ...ly used in the clock circuits LOGIC INPUT OUTPUT HIGH 0 0 Volts HIGH 0 0 Volts LOW 4 5 Volts LOW 4 5 Volts ELECTRICAL DESCRIPTION Input pulses to this circuit must have nominal positive voltage excur...

Page 436: ...st have nominal positive and negative voltages of 0 0 volts and 4 5 volts respectively Output signals from this circuit have nominal positive and negative static voltages of 0 0 volts and 13 5 volts r...

Page 437: ...ts respectively Output signals from this circuit have nominal positive and negative static voltage excursions of 0 0 and 13 5 volts respectively The maximum input current required is 2 25 milliamperes...

Page 438: ...TION Input signals to this circuit must have nominal positive and negative voltage excursions of 0 0 volts and 4 5 volts respectively The output voltage levels are identical to the input voltage level...

Page 439: ...cursions be tween 0 0 and 0 3 volts and nominal negative excursions between 3 6 and 5 4 volts The output voltage levels are identical to the input voltage levels The maximum input current required is...

Page 440: ...0 Volts LOW 3 0 Volts LOW 4 5 Volts ELECTRICAL DESCRIPTION Input signals to pin 12 must have nominal positive voltage excursions of 0 3 volts and nominal negative voltage excursions of 3 3 volts Input...

Page 441: ...ts ELECTRICAL DESCRIPTION Input signals to this circuit must have positive static vOltage excur sions of between 0 0 and 0 5 volts and negative static voltage excur sions of between 3 8 and 5 2 volts...

Page 442: ...e excur sions of 0 3 volts and nominal nega tive voltage excursions of 4 5 volts Output signals from this circuit will have nominal positive voltage ex cursions of 0 3 volts and a nominal static negat...

Page 443: ...plicable ELECTRICAL DESCRIPTION This module consists of a series of jumper wires used primarily for the transition from fast to slow interface in the input output section of the computer POWER REQUIRE...

Page 444: ...gure 8 30 TO PIN 12 TO PIN 13 0 1 0 FROM PIN 14 EXTERNAL CONNECTIONS ELECTRICAL DESCRIPTION The base of an externally mounted voltage control transistor is con nected to pin 11 of this module The emit...

Page 445: ...than 10 percent in the positive and negative IS volt supplies The level of detection may be adjusted to any level between 12 S and l3 S volts This module is designed to be used in conjunction with the...

Page 446: ...e The clear input is common for both flip flop circuits LOGIC INPUT OUTPUT HIGH 0 0 Volts HIGH 0 0 Volts LOW 4 5 Volts LOW 4 5 Volts ELECTRICAL DESCRIPTION Input signals to this circuit must have nomi...

Page 447: ...4 5 Volts ELECTRICAL DESCRIPTION Input signal to this circuit must have nominal positive excursions of 0 0 volts and nominal negative ex cursions of 4 5 volts The output voltage levels are identical...

Page 448: ...rformed by the flip flop Pins 10 11 and 14 are common to both of the flip flop circuits with pins 5 7 9 and 12 providing the unique in put signals LOGIC INPUT OUTPUT ELECTRICAL DESCRIPTION Input signa...

Page 449: ...licable ELECTRICAL DESCRIPTION The capacitors mounted on this module provide filter action for the voltages shown in parentheses Chassis maps indicate the location of the cards in the computer POWER R...

Page 450: ...supply a jumper network for external circuitry LOGIC INPUT OUTPUT HIGH 0 0 Volts HIGH n o Volts LOW 4 5 Volts LOW 4 5 Volts ELECTRICAL DESCRIPTION The time delay operates with input and output pulses...

Page 451: ...e ground lead of a panel lamp Pin 15 is common to all four output tran sistors and is grounded When a 4 5 volts is applied to any of the four driver inputs the respec tive output transistor will condu...

Page 452: ...ed for a steady state current of 4 amperes and will adjust for load changes from 1 3 to 6 amperes The sensing of temperature and or load variations affects a change in the for ward biasing of the inpu...

Page 453: ...igh LOGIC INPUT OUTPUT HIGH 0 0 Volts HIGH 0 0 Volts LOW 4 5 Volts LOW 7 5 Volts ELECTRICAL DESCRIPTION Input signals to this module must have nominal positive and negative voltage excursions of 0 0 a...

Page 454: ...onal 5 nanosecond delay LOGIC INPUT OUTPUT HIGH 0 0 Volts HIGH 0 0 Volts LOW 4 5 Vo lt s LOW 4 5 Volts ELECTRICAL DESCRIPTION This module composed of coils and capacitors operates in conjunction with...

Page 455: ...RICAL DESCRIPTION Input signals to this module must have nominal positive voltage excur sions of 0 0 volts and nominal nega tive voltage excursions of 4 5 volts The output voltage levels are identical...

Page 456: ...gh When at least one input is high the output will be a low LOGIC INPUT OUTPUT ELECTRICAL DESCRIPTION Pins 5 and 6 7 and 8 are shorted together internally POWER REQUIREMENTS PIN 1 2 3 4 HIGH 0 0 Volts...

Page 457: ...inputs to that element have a low the output signal input Anyone high input to Input signals must have nominal an element will result in a low output positive and negative voltage excursions from tha...

Page 458: ...ional delays are provided at taps in increments of 20 nanoseconds LOGIC INPUT OUTPUT HIGH 0 0 Volts HIGH 0 0 Volts LOW 4 5 Volts LOW 4 5 Volts ELECTRICAL DESCRIPTION This module composed of coils and...

Page 459: ...PUT OUTPUT HIGH N A HIGH N A LOW N A LOW N A ELECTRICAL DESCRIPTION This circuit is a detection device designed to sense voltage failures and tolerance decreases greater than 10 percent on the 4 5 vol...

Page 460: ...IGH N A LOW N A LOW N A ELECTRICAL DESCRIPTION The sensistor mounted on a memory stack controls the output voltage togive temperature compensation to the drive circuitry to ensure proper core operatio...

Page 461: ...h that input pin 12 is negative and input pin 13 is posi tive the output at pin 7 will reflect a positive excursion of approximately 0 5 rna If the polarity at the inputs is reversed or zero the outpu...

Page 462: ...pass on to another circuit With a 4 5 volts applied to input pin 5 the output transistors in this circuit are turned on and any positive potential applied to the output pins 14 and 15 is shunted direc...

Page 463: ...the tran sistor is cut off and current is in hibited LOGIC INPUT OUTPUT HIGH 0 0 Volts HIGH N A LOW 4 5 Volts LOW N A ELECTRICAL DESCRIPTION Input signals to this module must have nominal positive and...

Page 464: ...of the card When 4 5 volts is ap plied to both inputs of either AND gatesr the circuit will be enabled inducing a VOltage in the transformer secondary so the base of the output transistor will become...

Page 465: ...er normally used for amplifying small pulses from a core memory and contains three identical circuits and a common bias supply pin 5 The bias voltage applied at pin 5 is 10 volts With a positive volta...

Page 466: ...SYMBOLOGY 15 _ _ J i J J 2 4 Figure 8 52 NOT USED Figure 8 52 Jumper Switch Selector Module 7104010 Schematic Diagram ORIGINAL 8 59...

Page 467: ...14 _ v R3 13 J R4 12 _t j R5 I I _r R6 I 0 R7 9 _ R8 8 _ J R9 7 J RIO 6 j R II 5 4 L __4II__ ____ 4 5 V 3 i 15 V 2 i 15 V NOT USED I l Figure 8 53 Resistor Assembly Module 7109000 Schematic Diagram SY...

Page 468: ...low The low will be maintained while power is applied to the unit LOGIC INPUT OUTPUT HIGH HIGH LOW LOW ELECTRICAL DESCRIPTION This module contains a resistor capacitor network made up of two resistor...

Page 469: ...5 _ 14 t 13 4 12 ____L___ I I 10 9 8 I I I I I I 1 I I CI Il I RI 7 L A R2 6 _ _ C2 4 L 4 5V 15vJ NOT USED 2 L I 5 V SYMBOLOGY Figure 8 55 Capacitor Resistor Assembly Module 7109010 Schematic Diagram...

Page 470: ...ed this circuit performs an INVERTER function Unused pins are left open The module functions as a low input AND or high input OR by using either pin 43 44 or 46 for one input and either pin 51 52 or 5...

Page 471: ...3 8 1 6V 49 I 50 l CRI ICR2 iCR3 ICR4 ICR5 CR6 CR41 RI 6V j CR31 01 CI R36 R37 rR51 6V 3V CR56 CR57 eR66 S SIGNAL GROUND 15 20 CR7 TCR8 CRIO ICRIl TCRI2 CR43 03 CR45 05 CR47 I Q7 R33 R38 R41 R42 CR53...

Page 472: ...OSECONDS 32 PER TAP ONE u 34 MICROSECOND TOTAL eX 36 III 0 38 L J L J 37 0260 39 41 eX J 45 L J 47 0 51 53 54 52 48 46 42 40 35 33 31 30 25 24 22 18 16 SS J 14 12 10 6 97 5NS OV IUS 3 9 7 NS r 5 IUS T...

Page 473: ...e high level and then drops to the low level When the input to pin 26 is high or the inputs to pins 19 and 20 are high the 5 5 volt level propagates through the delay line reaching an output pin every...

Page 474: ...ard bias of transistor Q2b the error amplifier The collector current of transistor Q2b can decrease only if the collector current of transistor Q2a the reference amplifier increases This causes a larg...

Page 475: ...CR4 R22 l05 R2 1 R25 R4 lR5 CR2 CR3 u R23 RI5 CBO l 2 RI6 R7 r e S 020 6 4 RI7 03 RI8 04 I R6 3 S 2 38H 47H 554 56 L 3V 06 7 08 09 J1 t t t t t t t t R26 R27 R2B R29 R30 R31 R32 R33 R34 010 R35 R36 14...

Page 476: ...L2 L3 L4 L6 9 10 II 12 13 14 15 16 Figure 8 59 2 49 50 7 8 43 44 5 56 r iPI 3 3 2 CI f Clblc2 C2b n C3o r r C3b S SIGNAL GROUND 6V 3V 3V GRD TO PIN 14 ON Z12 TO PIN 7 ON Z12 L7 L8 L9 L10 LII L13 Ll4 L...

Page 477: ...60 17 TP5 EMITTER FOLLOWER GATED OUTPUT LC LEVEL CHANGE 9 EMITTER FOLLOWER TPI 4 3 4 0280 0280 INTEGRATED LOGIC CIRCUITS Figure 8 60 Emitter Follower Driver Amplifier Module 7500280 SYMBOLOGY 3 8 68...

Page 478: ...1 _ _ _ _ 1 _ _ _ _ 1 _ _ _ _ _ _ I_I _ _ I _ I _ _ I _ I _ _I _ I _ _ _ I _ I _ _ I _ I _ _ I _ I _ _I 4pl 5 06 07 08 6V 6V 6V 6V R5 R8 R7 R8 13 RI4 RI5 RI6 3V 3V 3V 3V I II I 2 4 5 8 9 II 12 I 2 4...

Page 479: ...2 6 DETECTOR 06 07 011 9 DETECTOR 15 VDC BLOCK DIAGRAM POWER FAILURE 5 TPI VOLTAGE FAILURE DETECTOR 01 POSITIVE VOLTAGES 02 NEGATIVE VOLTAGES PIN 3 15 VDC PIN 4 15 VDC PIN27 ISVDC PIN28 3 VDC PINI5 15...

Page 480: ...17f 18 21f ZZ I Z5 ZS 29f i 30f l nf i I THRUI 3Sf l 41fJ THRU 15V S SIGNAL GROUNDI NOT USED CRI3 15V R32 R49 48 51 15V 5Z 53 15V TP3 R22 R23 Figure 8 63 CR2 CR3 CR4 CR5 CR8 lCRS Q2 R21 CRI2 vS S R24...

Page 481: ...nitored by the voltage ratio detectors During normal operation transistor Ql is conducting and Q2 is biased to cutoff If a failure occurs in the 3 or 15 volt supply Q2 will become forward biased drivi...

Page 482: ...common to several bipolar switches Figure 8 64 shows the logic symbol of one bipolar switch and figure 8 65 shows the schematic diagram When the four inputs pins 17 18 20 and 28 are all high the bipo...

Page 483: ...CRI RI3 CR7 R26 CR8t CR9 r I 6V R33 R32 w t CRI7 CR27 CR2e CR29 CR39 CR40 CR41 16 9 II 12 Figure 8 65 20 19 22 2625 R2e R36 CR20 CRI9 CR31 CR42 CR43 CR44 10 3 4 44 32 34 31 R3e CR21 CR33 CR45 2827 30...

Page 484: ...he enabled second ary 8 MODULE 7500430 READ WRITE SELECTION MATRIX TRANSFORMER ASSEMBLY This module contains two identical circuits Each circuit has three enable inputs The output is half of the curre...

Page 485: ...set and input 35 is high All inhibit drivers are disabled when input pin 35 is low overload flip flop is clear a power failure exists or corresponding bit of Z register is set A sense inhibit line fr...

Page 486: ...R4 15V CRI r2 R7 RB 1 83 2 AI 1 fR13 fR14 R15 I4Q CR6 CRII 1 CR8 15V S Vs 15V 515443 R5 T3 2735 fRIB CR3 JCR4 R9 46 PI l C4blRI61 J R17 CR7 IS S tl5V I A2 R6 B5 Il 86 87 B8 B9 l BIO T2 BII 5 84 B R21...

Page 487: ...is applied across one of the pairs of input pins If the selected core does not switch no difference in voltage is developed across the two input pins The noise in each sense inhibit line is equal and...

Page 488: ...43 12 46 35 45 25 r TPI iii r 50T23 c 0430 c IJ40A c CI w 0 t J Q Z W w C CI 0 jj Iii c 0 c IJ J t Q I 15V_ W 34 33 WRITE READ 0100 E f__ tI_ 0100 E 50XXX READ 52XXX WRITE Figure 8 69 Logic Symbol of...

Page 489: ...CR6 ru l6 CRIOWII CR9 RI7 ISV 15V R20 R21 T 3 U 4 3 UAI B9rt B III 0 0 o 0 ll lliJ fii ll 0 0 0 U 03 llm IWl2 I CR4 3V A2 B4 RII t Q2 21 RI4 RIS 4 CR8 CR7 tCRI2 CRI3 RI9 I V t m t R23 T4 AI B7rul B9f...

Page 490: ...2 I 1 1 I I I 1 3 6 I I 721 __1 4 5 701 __ I 711 0650 I 731 __ t I I I 60A ___ 0650 I I I 4 5 I I I 25 26 21 22 17 18 II 12 23 24 19 20 15 16 9 10 35 CONDENSED lOGIC DIAGRAM Figure 8 71 Logic Symbol o...

Page 491: ...B A4 CRI3 6V B 15V A 15V B ____ A4 15V 4 TIIQ L B 6V A 6V A I I I _ _ I 15V A r R51 R5 54 _ n___ 1 B t ____ JNOT USED n n l n lJ n _ I 15V B IID 3V I I B4fn21AI I R42 JIIE A2 TI6 B4 A2 Ilf B4 AI 43r44...

Page 492: ...gram for this module A high input on either pin 5 11 20 or 22 will produce a low output on either pin 18 24 10 or 12 A high input on either pin 33 or 34 or on pin 51 or 54 will produce a low output on...

Page 493: ...48 37 38 55 56 PI TP7 TP9 R2 R3 R4 CI6 CI7 t5V CI8 Cig Te20 1 e2l Te22 vTC23 1 24 f 25 C26 ve27 uC28 C29 vC30 C31 T T T T T 3V C32 FC33 l C34 5 eRg CRII CRI3 CRI5 CRt1 CRI9 CR21 CR23 CR2S CR27 CR29 CR...

Page 494: ...SYMBOLOGY Figure 8 74 TPI RI 5 5V R7 7 4 5 5V ell R6 8 6 Figure 8 74 Module 7500670 Schematic Diagram II 51 54 46 19 24 Figure 8 75 Logic Symbol of Level Changer Amplifier Module 7500760 CHANGE 2 8 85...

Page 495: ...UNO 1 __________ __ 24 18 12 Figure 8 76 20 23 CR2 R4 15 1 R44 RSO TP2 I 10 19 30 27 U2 Z3 13 R5 6V 31 32 Lj12 Z3 R30 R6 6V JR31 2825 16 LlS Z3 10 R7 6V R32 54 51 34 33 36 40 48 _____ 1 1_1 ___ PI CR3...

Page 496: ...2 02 6 4 12 10 P I TPI P 85XOO 0780 IJ43B 3 Figure 8 77 Logic Symbol of Current Regulator Circuit on 7500780 Module 31 32 21 22 Figure 8 78 Logic Symbol of Noninverting Amplifier Driver Module 7500900...

Page 497: ......

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