Spectrum M2i.3010, Hardware Manual

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84 M2i.30xx / M2i.30xx-exp Manual
Internally generated sample rate Clock generation
Maximum internal sampling rate in MS/s
The interlace mode (160/200 MS/s) is only working with a sampling rate programmed exactly to the men-
tioned value of 160 MS/s or 200 MS/s. It is not possible to use the interlace mode with a sampling rate that
is set to anything inbetween Interlace and Interlace/2, for example 140 MS/s!
Using plain Quartz1 without PLL
In some cases it is useful for the application not to have the on-board PLL activated. Although the PLL used on the Spectrum boards is a low-
jitter version it still produces more clock jitter than a plain quartz oscillator. For these cases the Spectrum boards have the opportunity to switch
off the PLL by software and use a simple clock divider.
The Quartz1 used on the board is similar to the maximum sampling rate the board can achieve. As with internal PLL mode it’s also possible
to program the clock mode first, set a desired sampling rate with the SPC_SAMPLERATE register and to read it back. The driver will internally
set the divider and find the closest matching sampling rate. The result will then again be the best matching sampling rate.
If a sampling rate is generated internally, you can additionally enable the clock output. The clock will be available on the external clock
connector and can be used to synchronize external equipment with the board.
Using plain Quartz2 without PLL (optional)
In some cases it is necessary to use a special frequency for sampling rate generation. For these applications all cards of the M2i series can
be equipped with a special customer quartz. Please contact Spectrum for details on available oscillators. If your card is equipped with a
second oscillator you can enable it for sampling rate generation with the following register:
In addition to the direct usage of the second clock oscillator one can program the internal clock divider to use slower sampling rates. As with
internal PLL mode it’s also possible to program the clock mode first, set a desired sampling rate with the SPC_SAMPLERATE register and to
read it back. The result will then again be the best matching sampling rate.
If a sampling rate is generated internally, you can additionally enable the clock output. The clock will be available on the external clock
connector and can be used to synchronize external equipment with the board.
activated Channels
M2
i.
30
10
M2
i.
30
11
M2
i.
30
12
M2
i.
30
13
M2
i.
30
14
M2
i.
30
15
M2
i.
30
16
M2
i.
30
20
M2
i.
30
21
M2
i.
30
22
M2
i.
30
23
M2
i.
30
24
M2
i.
30
25
M2
i.
30
26
M2
i.
30
27
M2
i.
30
31
M2
i.
30
33
Ch0 Ch1 Ch2 Ch3
X 80 40 80 40 80 160 160 105 50 105 50 105 200 200 105 62.5 62.5
X n.a. 40 80 40 80 80 80 n.a. 50 105 50 105 105 105 105 62.5 62.5
X n.a. n.a. n.a. 40 80 n.a. 80 n.a. n.a. n.a. 50 105 n.a. 105 n.a. n.a. 62.5
X n.a. n.a. n.a. 40 80 n.a. 80 n.a. n.a. n.a. 50 105 n.a. 105 n.a. n.a. 62.5
X X n.a. 40 40 40 40 80 40 n.a. 50 50 50 50 105 50 105 62.5 62.5
X X n.a. n.a. n.a. 40 80 n.a. 80 n.a. n.a. n.a. 50 105 n.a. 105 n.a. n.a. 62.5
X X n.a. n.a. n.a. 40 80 n.a. 80 n.a. n.a. n.a. 50 105 n.a. 105 n.a. n.a. 62.5
X X n.a. n.a. n.a. 40 80 n.a. 80 n.a. n.a. n.a. 50 105 n.a. 105 n.a. n.a. 62.5
X X n.a. n.a. n.a. 40 80 n.a. 80 n.a. n.a. n.a. 50 105 n.a. 105 n.a. n.a. 62.5
X X n.a. n.a. n.a. 40 40 n.a. 40 n.a. n.a. n.a. 50 50 n.a. 50 n.a. n.a. 62.5
X X X X n.a. n.a. n.a. 40 40 n.a. 40 n.a. n.a. n.a. 50 50 n.a. 50 n.a. n.a. 62.5
Register Value Direction Description
SPC_CLOCKMODE 20200 read/write Defines the used clock mode
SPC_CM_QUARTZ1 2 Enables Quartz1 for sample clock generation
Register Value Direction Description
SPC_CLOCKOUT 20110 read/write Enables clock output on external clock connector.On A/D and D/A cards only possible with internal
clocking.
SPC_CLOCKOUTFREQUENCY 20111 read Allows to read out the frequency of an internally synthesized clock present at the clock output.
Register Value Direction Description
SPC_CLOCKMODE 20200 read/write Defines the used clock mode
SPC_CM_QUARTZ2 4 Enables optional quartz2 for sample clock generation
Register Value Direction Description
SPC_CLOCKOUT 20110 read/write Enables clock output on external clock connector.On A/D and D/A cards only possible with internal
clocking.
SPC_CLOCKOUTFREQUENCY 20111 read Allows to read out the frequency of an internally synthesized clock present at the clock output.