BIOS Setup Utility
SY-K7ADA XP
60
CHIPSET FEATURES SETUP (Continued)
CHIPSET
FEATURES
Setting
Description
Note
Auto (By SPD)
2.5 (DDR) / 3 (SDR)
Default
DRAM CAS
Select
2 (DDR) / 2 (SDR)
When synchronous
DRAM is installed, the
number of clock cycles of
CAS latency depends on
the DRAM timing. Do not
reset this field from the
default value specified by
the system designer.
Auto (By SPD)
Failsafe
Slow
Normal
Default
Fast
Ultra
Ultra2
This item allow you to
control the DRAM timing.
7.16 MHz
CLK2/2
CLK2/3
CLK2/4
Default
CLK2/5
DARM
Performance
AT Bus Clock
CLK2/6
This item allow you to
control the ISA Bus clock.
Disabled
Default
System BIOS
Cacheable
Enabled
The ROM area
F0000H-FFFFFH is
cacheable.
