27
D-NS707F
5-9. IC PIN FUNCTION DESCRIPTIONS
Pin No.
Pin Name
I/O
Description
1
XRAS
O
Row address strobe signal output to the D-RAM
2
XWE
O
Data input enable signal output to the D-RAM
3 to 6
D1, D0, D3, D2
I/O
Two-way data bus with the D-RAM
7
DCLK
O
Not used (open)
8
DCKE
O
Not used (open)
9
XCAS
O
Column address strobe signal output to the D-RAM
10
WFCK
O
Not used (open)
11 to 13
A9 to A7
O
Address signal output to the D-RAM
14
DVSS
—
Ground terminal (for D-RAM interface)
15 to 17
A6 to A4
O
Address signal output to the D-RAM
18
XRDE
I
D-RAM read enable signal input from the MP3 decoder (IC701)
19
VDD0
—
Power supply terminal (digital system)
20
CLOCK
I
Serial data transfer clock input from the system controller (IC801)
21
SDTO
I
Serial data input from the system controller (IC801)
22
SENS
O
Serial data output to the system controller (IC801)
23
XLAT
I
Serial data latch pulse signal input from the system controller (IC801)
24
XSOE
I
Serial data output enable signal input from the system controller (IC801)
25
SYSM
I
Analog muting on/off control signal input from the system controller (IC801)
26
WDCK
O
Not used (open)
27
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller (IC801)
28
XRST
I
Reset signal input from the system controller “L”: reset (IC801)
29
PWMI
I
Not used (fixed “L” )
30
XQOK
I
Not used (fixed “L” )
31
XWRE
I
Not used (fixed “L” )
32
R8M
O
System clock output to the system controller (IC801)
33
VSS0
—
Ground terminal (digital system)
34
SQCK
I
Not used (fixed “H” )
35
SCLK
I
Not used (fixed “H” )
36
SQSO
O
Not used (open)
37
XEMP
O
Not used (open)
38
XWIH
O
Not used (open)
39
SBSO
O
Not used (open)
40
EXCK
O
Not used (fixed “L” )
41
XTSL
I
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688MHz (fixed at “L” in this set)
42
HVSS
—
Ground terminal (for headphone)
43
HPL
O
Not used (open)
44
HPR
O
Not used (open)
45
HPVDD
—
Power supply terminal (for headphone)
46
XVDD
—
Power supply terminal (for master clock)
47
XTAI
I
System clock input terminal (16.9344 MHz)
48
XTAO
O
System clock output terminal (16.9344 MHz)
49
XVSS
—
Ground terminal (for master clock)
50
AVDD1
—
Power supply terminal (analog system)
51
AOUT1
O
L-ch analog audio signal output
52
VREFL
O
L-ch reference voltage output terminal
• IC601 CXD3039AR
(RF AMP, DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, D-RAM CONTROLLER)
