Sony U-Ceiver ICB-U655, Service Manual

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– 19 – – 20 – – 21 – – 22 –
• Waveforms
– RF Board –
1 IC2 1 (OSC IN) (TX mode)
500 mV/DIV, 20 ns/DIV
2 IC3 1 (OSC IN) (TX mode)
500 mV/DIV, 20 ns/DIV
4 IC101 %∞ (XT1) (RX/TX mode)
1 V/DIV, 10 µs/DIV
5 IC101 %• (X1) (RX/TX mode)
1 V/DIV, 100 ns/DIV
– MICRO COMPUTER Board –
3 IC109 2 (XTAL) (TX mode)
1 V/DIV, 500 ns/DIV
940 mVp-p
47.1 ns
1.6 Vp-p
47.1 ns
2.7 Vp-p
1
µ
s
2.5 Vp-p
30.5 µ s
2.3 Vp-p
238 ns
• IC Block Diagrams
– RF Board –
IC1 µPC2757T-E3
IF OUT
VCC
POWER
SAVE
RF IN
GND
LO IN
6
5
4
1
2
3
IC3 MB15E03LPFV1-G-BND-ER
LOCAL
OSCILLATION
RSSI
QUADRATURE
DETECTION
1
2 3
4
5 6 7 8
9 10 16 15 14 13 12 11
NOISE
AMP
FILTER
AMP
IF AMP
BUFFER
MIXER
DETECTOR
NOISE
COMPARATOR
MIX IN GND N-REC N-DET RSSI IF OUT QUAD AF OUT
OSC IN
OSC OUT MIX OUT
VCC IF IN DEC
FIL OUT
FIL IN
L.P.F
fr
fp
VP
VCC
DO
φ
R
φ
P
SUPER
CHARGER
CONTROL
1 BIT
POWER
SAVE
CIRCUIT
PHASE
COMPARATOR
DIGITAL LOCK
DETECT
CIRCUIT
SELECT
CIRCUIT
PRESCALER
64/65
128/129
CRYSTAL
OSCILLATOR
CIRCUIT
5
OSC OUT 2
4
3
OSC IN 1
XFIN 7
GND 6
FIN 8
16
15
LD/FOUT 14
LE
11
DATA 10
CLOCK 9
PS 12
ZC 13
14 BIT LATCH
BINARY 14 BIT
REFERENCE COUNTER
3 BIT LATCH
SW FC LDS
11 BIT LATCH 7 BIT LATCH
BINARY 7 BIT
SWALLOW
COUNTER
BINARY 11 BIT
PROGRAMMABLE
COUNTER
19 BIT
SHIFT REGISTER
CNT
IC2 TA31136FN
– MICRO COMPUTER Board –
IC102 NJM2070M
NC
+IN
–IN
GND
NC
VCC
OUTPUT
POWER GND
2
3
4
1
6
5
7
8
BIAS
+
–
IC109 MX165CDW-TR
CLK/XTAL
CLK/XTAL
CLK
CLK
TONE IN
VREF
D0 – D10
A0 – A5
VDD
XTAL/CLK
XTAL
D5/SERIAL EN 1
D4/SERIAL EN 2
D3/SERIAL DATA
D1/DATA IN 1
D0/DATA IN 0
D2/SERIAL CLK
VSS
DECODE
COMPARATOR REF.
DIGITAL
INTERFACE &
CLOCK
GENERATOR
TONE
ROM
TONE
DECODE
FILTER
TONE IN
PULSE
AUDIO
FILTER
TONE OUT
FILTER
TONE DECODE
LOGIC
24
RX AUDIO IN 23
TX AUDIO IN 22
BIAS 21
TX AUDIO OUT 20
RX AUDIO OUT 19
PTL 18
TX TONE OUT 16
RX TONE OUT 15
17
1
2
4
5
6
7
8
9
10
11
12
3
+
–
+
–
LOAD/LATCH
RX/TX
13 RX TONE DET OUT
14
DECODE
COMPARATOR IN
•
MICRO COMPUTER BOARD IC101
µ
PD753012AGC-F00-3B9 (SYSTEM CONTROLLER)
Pin No. Pin Name I/O Description
1 to 12 LCD6 to LCD17 O Segment drive signal output to the liquid crystal display (LCD101)
13 STRB O Serial data latch pulse output to the CTCSS encoder/decoder (IC109)
14 to 20
—
—
Not used (open)
21, 22 LCD18, LCD19 O Common drive signal output to the liquid crystal display (LCD101)
23, 24 — — Not used (open)
25 BIAS O Liquid crystal display drive bias control output terminal
26 to 28 VLC0 to VLC2 — Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
29 LED O LED drive signal output for the LCD back light on/off control “L”: LED on
30 — — Not used (open)
31 POWER SAVE O
Power save control signal output terminal
“L”: power on, “H”: power off (when receive, squelch on mode)
32 TX/RX O
Power supply control signal output for the transmit/receive selection
“L”: receive, “H”: transmit
33 VSS — Ground terminal
34 AF POWER O Power supply on/off control signal output of the power amplifier (IC102) “L”: power on
35 MUTE O
Muting on/off control signal output for the receiver system “L”: muting on
36 TX MUTE O Muting on/off control signal output for the transmit system “H”: muting on
37 V1-OUT O Control signal output for the battery detection circuit
38 POWER I POWER switch (S101) input terminal “L” is input when key pushing
39 PTT I Transmit detection signal input terminal
40 T/C I CH/GROUP switch (S102) input terminal “L”: CH, “H”: GROUP
41 — — Not used (open)
42
P10
I
Tone detection signal input terminal
43 LD I Synthesizer unlock detection signal input from the PLL frequency synthesizer (IC3)
44 LBL I LIGHT/BATT H switch (S103) input terminal “H” is input when key pushing
45
SQL
I
Squelch detection signal input from the TA31136FN (IC2) AF signal mute when “L” input
46 CH (+) I CH (+) switch (S104) input terminal “L” is input when key pushing
47 MODE I MODE switch (S105) input terminal “L” is input when key pushing
48 MONITOR I Not used (open)
49 — — Not used (open)
50 CH (–) I CH (–) switch (S106) input terminal “L” is input when key pushing
51 BEEP O Beep sound signal output to the power amplifier (IC102)
52
1kHz OUT
O
1 kHz signal output for the search mode
53 MAIN +B O
Main system power supply (+2.9V) on/off control signal output terminal
“L”: power off, “H”: power on
54
VDD
—
Power supply terminal (+3V)
55 XT1 I Sub system clock input terminal (32.768 kHz)
56 XT2 O Sub system clock output terminal (32.768 kHz)
57
IC
—
Internal connection terminal (connected to power supply (+3V))
58 X1 I Main system clock input terminal (4.194304 MHz)
59 X2 O Main system clock output terminal (4.194304 MHz)
60 LE O Serial data latch pulse output to the PLL frequency synthesizer (IC3)
61 DATA O Serial data output to the CTCSS encoder/decoder (IC109) and PLL frequency synthesizer (IC3)
62 CLOCK O
Serial data transfer clock signal output to the CTCSS encoder/decoder (IC109) and PLL
frequency synthesizer (IC3)
63 CARIA O Transmit system power supply on/off control signal output terminal “H” active
5-4. IC PIN FUNCTION DESCRIPTION