TAD-M30
— 7 —
— 8 —
3-2. BLOCK DIAGRAM — DIGITAL SECTION —
: DIGITAL
65
CCB/SUB
• Signal Path
• R-CH is omitted
: ANALOG
DIGITAL
IN
IC101
OPTICAL
IN
COAXIAL
3
OPTICAL
OUT
J101
DIGITAL
OUT
IC102
3
3
5
6
2
IC105
SELECTOR
IC108
1
A1
5
B1
6
7
Y1
S
DIR
IC201
35
D OUT
D IN
47
11
40
41
42
30
38
34
BCK
36
LRCK
28
CLK
RST
SWDT
XLAT
SCLK
ERROR
SRDT
RST
SWDT
XLAT
SCLK
ERROR
SRDT
X191
12.288MHz
1
7
6
2
IC191
27
26
XO
XI
X201
24.576MHz
4
QB1
CK1
1
CLOCK
COUNTER
IC112
3
5
SCK
26
DIGITAL SIGNAL PROCESSOR
IC118
6
2
1
7
3
5
6
2
1
7
5
6
3
5
IC110
IC109
IC107
IC110
IC111
1
7
IC111
57
56
51
55
27
SDI0
SDI1
SCKR
WSR
EXTAL
PLL
AUDIO
I/F
47
SDO0
46
SDO1
49
SCKT
50
WST
MEMORY
HOST I/F
DSP
MISO
35
SS
42
HREQ
43
MOSI
41
RESET
36
SCK
26
DIGITAL SIGNAL PROCESSOR
IC119
57
56
51
55
27
SDI0
SDI1
SCKR
WSR
EXTAL
PLL
AUDIO
I/F
47
SDO0
46
SDO1
MEMORY
HOST I/F
DSP
MISO
35
SS
42
HREQ
43
MOSI
41
RESET
36
SCKT
49
WST
50
GPIO0
76 75 74
GPIO1
GPIO2
47
SDO2
DSP
13
15
17
21
.
22
25
20
.
18
16
.
11
14
7
.
5
.
3
71
69
67
.
65
62
.
80
MCA
77
MRD
78
MWR
MA0
MA15
MD0
MD7
MD0
MD7
A0
A15
A16
12
OE
24
R/W
29
S RAM
IC120
23
25
28
31
.
2
.
11
.
DATA (FRONT)
DATA (C/S)
DATA (REAR)
BCK
9
8
IC110
11
10
IC110
13
12
IC110
LRCK
CLK (FRONT)
MUTE
CLK (C/S)
CLK (REAR)
2
RF RESET
76
SWDT
77
XLA
T
78
SCLK
67
ERROR
75
SRDT
20
RESET
RST
SWDT
XLA
T
SCLK
ERROR
SRDT
19
MOSI
21
MISO
22
CLOCK
18
SS
17
HREQ
29
LOW FREQ IED 0
26
RESET
25
MOSI
27
MISO
28
CLOCK
24
SS
23
HREQ
30 31
LOW FREQ IED 1
LOW FREQ IED 2
SYSTEM CONTROL
IC151(1/2)
16
8
16
8
