48
Pin No.
91
92 – 94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117 – 120
I/O
—
O
O
I
I
O
I
O
—
—
—
—
I/O
I
I
I
O
O
—
—
I
I
I
I
I
Description
Ground
External RAM address output
Not used
Test data input “L” = normal “H” = test (Connecting to ground)
PLL input frequency select “L” = 256Fs “H” = 128Fs (Connecting to ground)
PLL output frequency select “L” = 768Fs “H” = 1024Fs (Connecting to ground)
Master clock input
Master clock output (Not used)
Ground
+3.3V
Ground for PLL cell
VDD for PLL cell
PLL output/test clock input
PLL cell oscillation enable “L” oscillation enable “H” oscillation stop (Connecting to ground)
Test data input “L” = normal “H” = test (Connecting to ground)
Frequency counter input (Connecting to ground)
LRCK0 divider output
BCK0 divider output
Ground
+3.3V
BCK input
BCK input
LRCK input
LRCK input
Serial data input
Pin Name
V
SS
0
EA13 – EA15
EA16
TSTA
PLDIVF
PLDIVB
CLKI
CLKO
V
SS
1
V
DD
0
AV
SS
AV
DD
PLLCK
XPLLEN
TST
LRCT
LROUT
BKOUT
V
SS
2
V
DD
1
BCK0
BCK1
LRCK0
LRCK1
SIA – SID
Summary of Contents for TA-VA777ES
Page 13: ...TA VA777ES 13 13 3 7 SCHEMATIC DIAGRAM AUDIO SECTION See page 43 44 for IC Block Diagrams ...
Page 15: ...TA VA777ES 15 15 3 9 SCHEMATIC DIAGRAM VIDEO SECTION See page 44 45 for IC Block Diagrams ...
Page 39: ...TA VA777ES 39 39 3 34 SCHEMATIC DIAGRAM SPEAKER TERMINAL SECTION J1301 4P ...
