Sony STR-SL5, Service Manual

Page: 24 / 38

24
STR-KSL5
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64-66
67-69
70
71
72-75
76
77-80
81
82-85
86
87
88
89
90
91
92-97
98,99
100
101
102-105
106
107,108
109,110
111
112
113
114
115
116
117-119
120
Pin Name
PAGE0
BOOT
BTACT
BST
MOD1
MOD0
EXLOCK
VDDI
VSS
A17
A16
A15-A13
GP10-GP8
VDDI
VSS
D15-D12
VDDE
D11-D8
VSS
A9-A10
TDO
TMS
XTRST
TCK
TDI
VSS
A8-A3
D7,D6
VDDI
VSS
D5-D2
VDDE
D1,D0
A2,A1
VSS
A0
PM
SD13
SD14
SYNC
VSS
VDDI
I/O
O
I
O
I
I
I
I
—
—
O
O
O
I/O
—
—
I/O
—
I/O
—
O
O
I
I
I
I
—
O
I/O
—
—
I/O
—
I/O
O
—
O
I
I
I
I
—
—
Description
ERAM page switch (TP1212)
Not used (Ground)
Boot mode status display signal (TP1213)
Boot strap signal input from the system control (IC1601)
Setting for 256fs (pllx9) (pull up)
Setting for single chip mode (pull down)
Lock signal input terminal
+2.5V
Ground terminal
External memory address (TP1214)
External memory address (TP1215)
Address signal output to the SRAM (IC1202)
External memory data I/O general purpose port terminal GP
+2.5V
Ground terminal
SRAM (IC1202) data signal I/O terminal
+3.3V
SRAM (IC1202) data signal I/O terminal
Ground terminal
Address signal output to the SRAM (IC1202)
Simple emulation data output (TP1216)
Simple emulation data entry beginning and the end terminal (TP1217)
Asynchronous simple BREAK input terminal of emulation (TP1218)
Simple emulation clock input (TP1219)
Simple emulation data entry (TP1220)
Ground terminal
Address signal output to the SRAM (IC1202)
SRAM (IC1202) data signal I/O terminal
+2.5V
Ground terminal
SRAM (IC1202) data signal I/O terminal
+3.3V
SRAM (IC1202) data signal I/O terminal
Address signal output to the SRAM (IC1202)
Ground terminal
Address signal output to the SRAM (IC1202)
PLL initialization input from the system control (IC1601)
Data entry terminal (TP1221)
Data entry terminal (TP1222)
Synchronization / asynchronous selection terminal (L:Sync. H:Async.)
Ground terminal
+2.5V