31
STR-KS500
Pin No.
Pin Name
I/O
Description
52
RDS CLK
I
RDS interrupt clock signal input from the tuner
53
RDS DATA
I
RDS serial data input from the tuner
54
SIRCS
I
Sircs signal input from the remote control receiver
55
FUSE DETECT
I
Fuse detection signal input terminal "H": fuse detect
56
POWER KEY
I
Power key input terminal "L": power on
57
NC
O
Not used
58
POW_MUTE
O
Power muting control signal output terminal Not used
59
VOL (B)
I
Jog dial pulse input from the rotary encoder (B phase input) (for MASTER VOLUME)
60
VOL (A)
I
Jog dial pulse input from the rotary encoder (A phase input) (for MASTER VOLUME)
61
DIN
O
Serial data output to the fluorescent indicator tube driver
62
CLK
O
Serial data transfer clock signal output to the fluorescent indicator tube driver
63
FL_STB
O
Strobe signal output to the fluorescent indicator tube driver
64
MUTE
O
Muting on/off control signal output to the tuner "L": muting on
65
STEREO
I
FM stereo detection signal input from the tuner "L": stereo
66
TUNED
I
Tuned detection signal input from the tuner "L": tuned
67
PROTECTOR
I
Protect on/off detection signal input from the protect circuit "H": protect on
68
SLATCH
O
Serial data latch pulse signal output to the tuner
69
DO
I
Serial data input from the tuner
70
FRONT RELAY
O
Relay drive signal output (for front speaker) "H": relay on
71
CENTER RELAY
O
Relay drive signal output terminal (for center) "H": relay on
72
REAR RELAY
O
Relay drive signal output (for surround (rear)) "H": relay on
73, 74
F_CTRL1,
F_CTRL2
O
Fan motor control signal output terminal
75
FAN_CLK
I
Fan motor feedback clock signal input terminal
76
FAN_DETECT
I
Fan motor speed level detection signal input terminal
77
RSTX
I
System reset signal input from the reset signal generator "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
78
POWER RELAY
O
Relay drive signal output terminal (for main power) "H": relay on
79
X1A
O
Sub system clock output terminal Not used
80
X0A
I
Sub system clock input terminal Not used
81
VSS
-
Ground terminal
I
Main system clock input terminal (24 MHz)
Main system clock output terminal (24 MHz)
-
Power supply terminal (+3.3V)
-
Not used
-
Not used
-
Not used
Signal selection signal output terminal Not used
-
Not used
System reset signal output to the digital audio interface receiver "L": reset
94
CKSEL1
O
Output clock selection signal output terminal Not used
95
CLK
O
Clock signal output to the digital audio interface receiver
96
CE
O
Chip enable signal output to the digital audio interface receiver
97
DI
O
Write data output to the digital audio interface receiver
98
DO
I
Read data input from the digital audio interface receiver
99
ERROR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
100
XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
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