– 33 –
• IC Block Diagrams
– MAIN BOARD –
IC1
BU1924
IC300
CXA8079S
QUALITY BIT
GENERATOR
DEFFERENTIAL
DECODER
BIPHASE
SYMBOL
DECODER
OSCILLATOR
AND
DIVIDER
57kHz
BANDPASS
(8th ORDER)
CONTAS LOOP
VARIABLE AND
FIXED DIVIDER
REFERENCE
VOLTAGE
ANTI-
ALIASING
FILTER
CLOCKED
COMPARATOR
TEST LOGIC AND OUTPUT
SELECTOR SWITCH
RECONSTRUCTION
FILTER
14
15
16
13
12
11
10
9
3
2
1
4
5
6
7
8
CLOCK REGENERATION
AND SYNC
VP1
RDCL
TS7
OSCO
OSCI
V
DDD
V
SSD
TEST
TSTL
D
QUAL
RDDA
Vref
MUX
V
DDA
V
SSA
CIN
SCOUT
48
VCS2
VCS1
VCS-TH
L+R-RCT
L-R-RCT
DCUT
DCUT
R-BPF3
R-BPF2
R-BPF1
CT
-OUT2
CT
-IN2
MIXOUT
C-OUT
S-OUT
R-OUT
L-OUT
VCC
CM-CAP
FCC-IN2
ENABLE
D
ATA
CLK
OSC1
NS-BPF1
NS-BPF2
VREF
S-DCUT
C-DCUT
L-DCUT
R-DCUT
VREF-BUF
L-IN
R-IN
GND
CT
-OUT1
CT
-IN1
FCC-IN1
L-BPF1
L-BPF2
L-BPF3
DCUT
DCUT
R-RCT
L-RCT
VLR-TH
VLR1
VLR2
47 46 45
44 43
42
41
40
39
38
37
36
35
34
33
32
31
30 29 28
L+R-RECT
27
26
25
P.S
VCS-LOG
OSC
DEC
N-GEN
N-BPF
N-OH
DIV
BAL-DET
BALCONT
VREF
VR
VR
VCRX8
COMB-NET
CMODE
SMUTE
C-TRIM
P
B
P
B
P
B
P
B
R
B
R
B
R-B.P.F.
L-B.P.F.
L-R-RECT
R-RECT
L-RECT
VLR-LOG
DUAL-TIME
P.S
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
