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STR-DA3200ES/DG1000
42
42
STR-DA3200ES/DG1000
6-12. SCHEMATIC DIAGRAM – DIGITAL Board (2/5) –
•
See page 64 for Waveforms.
•
See page 92 for IC Block Diagrams.
R2079
R2057
Q2002
R2061
R2033
R2044
R2058
R2082
R2086
R2038
R2034
R2025
R2022
R2053
R2023
R2027
R2026
R2024
R2006
R2008
R2003
R2004
R2005
R2055
R2050
R2007
R2084
R2087
R2064
R2097
R2018
R2416
R2036
C2050
C2060
EB2001
EB2002
C2029
C2039
C2016
C2030
C2040
C2048
C2049
C2054
C2052
C2015
FB2006
Q2005
IC2022
C2085
C2088
C2057
C2059
C2090
C2089
CN2004
C2092
C2091
C2035
C2038
C2078
D2002
D2008
IC2006
FB2020
FB2009
FB2010
X2001
FB2005
Q2004
C2047
L2002
100
33k
DTC-144EKA
10k
1M
100
10
100
100
100
100
100
100
220
10k
10k
10k
10k
10k
10k
100
100
100
220
100
1k
1k
1M
470
0
47
100
220
100 16V
470
16V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.022
0.01
21B471
2SC2712
TC7WH74FU
0.1
10
50V
220
10V
2.2
50V
0.1
10
50V
50P
10 50V
0.1
12p
12p
470p
1SS355
RB051L-40
LC89057W-VF4A-E
0
0
24.576MHz
DTC-144EKA
470
16V
A1
RDATA0
DIR ERR
DIR XMODE
DIR CE
DIR DO
DSP_MOSI
DSP_SPICLK
SF_CPU_CE
DSP_MISO
DSP_INT
DSP_SPIDS
DSP_RESET
SF_DSP_MAS
DSP3.3V
D+3.3V
DGND
COM1-DATA
COM1-CLK
DO1
DO2
DO3
DO4
BCKO
LRCKO
D/A MCK
DSP 2.5V
ERROR
DIR CKST
ERROR
CKA
SI_B
SI_C
SI_E
SI_D
BCK1
R
X
O
U
T
R
X
0
R
X
4
R
X
3
R
X
2
RBCK
U
I
COM1 CLK
COM1 DATA
RLRCK
RMCK
DIR ERR1
X
M
C
K
D
IR
C
K
S
T
RDATA0
SI_A
SI_A
DIR ERR
DO2
DO4
LRCKO
DSP_INT
SF_CPU_CE
DSP_MOSI
DSP_MOSI
DO1
DO3
BCKO
DSP_RESET
D
R
I_
N
O
N
A
U
DRI_NONAU
DSP_SPIDS
DSP_MISO
DSP_SPICLK
D/A MCK
DIR DO
DIR CE
DIR XMODE
MCK1
MCK1
DSP_RESET
DSP_SPIDS
DSP_MISO
DSP_SPICLK
DIR ERR
DIR CKST
RDATA0
ERROR
DIR XMODE
COM1-CLK
DIR CE
DIR DO
COM1-DATA
SF_DSP_MAS
DSP_MOSI
SF_CPU_CE
DSP_INT
BCKO
D/A MCK
DO1
DO2
DO3
DO4
LRCKO
GND
GND
GND
GND
GND
GND
BCK
LRCK
SI_A
SI_B
SI_C
SI_D
SI_E
DSP_BCK
SO_A
SO_E
SO_B
SO_C
SO_D
DSP_RESET
∗
DSP_INT
DIR_RERR
SF_DSP_MAS
SF_CPU_CE
∗
DSP_SPIDS*
DSP_MISO
DSP_MOSI
PWR_INT
PWR_EXT
PWR_EXT
PWR_EXT
PWR_EXT
PWR_INT
PWR_INT
PWR_INT
GND
GND
DSP_SPICLK
DSP_LRCK
GND
GND
RESERVED
RESERVED
RESERVED
DIR_NONAU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
GND
GND
GND
MCK
(2/5)
V
C
C
Q
C
K
D
G
N
D
Q
C
LR
P
R
DO
DI
CE
CL
XMODE
DGND
DVDD
TBCK/PIO1
TLRCK/PIO2
TDATA/PIO3
TXO/PIOEN
TMCK/PIO0
R
X
O
U
T
R
X
0
R
X
1
R
X
2
R
X
3
D
G
N
D
D
V
D
D
R
X
4
R
X
5
/V
I
R
X
6
/U
I
D
V
D
D
D
G
N
D
LPF
AVDD
AGND
RMCK
RBCK
DGND
DVDD
RLRCK
RDATA
SBCK
SDIN
SLRCK
R
E
R
R
E
M
P
H
A
/U
O
D
G
N
D
D
V
D
D
X
IN
X
O
U
T
X
M
C
K
D
V
D
D
D
G
N
D
A
U
D
IO
/V
O
C
K
S
T
IN
T
SHIFT
(CHASSIS)
DIGITAL AUDIO INTERFACE
Q2002,2004,2005
PLL CLOCK SELECT
REGISTER
0.47
µ
H
(Page 41)
(Page
44)
(Page 43)
(Page 44)
(Page 45)
(Page 49)
Summary of Contents for STR-DA3200ES - Es Receiver
Page 167: ...167 STR DA3200ES DG1000 MEMO ...