Sony STR-DA2ES - Fm Stereo/fm-am Receiver, Service Manual, Page: 66 / 110

66
STR-DA2ES/DB1080
Pin No.
Pin Name
I/O Description
46 LRCK EN O Signal selection signal output “L”: boot strap signal, “H”: L/R sampling clock signal
47 ERROR I Error signal input from the audio digital signal processor 2
48 NC I Not used
49 SUB.T.PORT O Sub power on/off signal output “H”: power on
50 SP B I
Front B speaker on/off switch input terminal “L”: speaker on
(except STR-DB1080: E model)
51 GND — Ground terminal
52 MD2 O Setting terminal for the CPU operation mode Fixed at “L” in this set
53, 54 MD1, MD0 O Setting terminal for the CPU operation mode Fixed at “H” in this set
55 RSTX I
System reset signal input “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
56 VCC — Power supply terminal (+3.3V)
57 X1 O Main system clock output terminal (16.5 MHz)
58 X0 I Main system clock input terminal (16.5 MHz)
59 VSS — Ground terminal
60 STOP I Sub power voltage detection signal input
61 RDS CLK
I
RDS serial data transfer clock signal input from the tuner unit
(STR-DB1080: AEP and UK models only)
62 POWER I I/ 1 key input terminal
63 MBUS TV I TV and SAT signal input terminal (STR-DA2ES only)
64 MBUS DVD I DVD and LD signal input terminal (STR-DA2ES only)
65 MBUS VIDEO I VIDEO signal input terminal (STR-DA2ES only)
66 SIRCS I Sircs signal input
67 DIR ERROR I PLL lock error signal and data error flag input from the digital audio interface receiver
68 VCC — Power supply terminal (+3.3V)
69 XSTATE I Source clock selection monitor input from the digital audio interface receiver
70 DATA0 I Audio serial data input from the digital audio interface receiver
71 XMODE O System reset signal output to the digital audio interface receiver “L”: reset
72 CKSEL1 O Output clock selection signal output to the digital audio interface receiver
73 CLK O Clock signal output to the digital audio interface receiver
74 CE O Chip enable signal output to the digital audio interface receiver
75 DI O Write data output to the digital audio interface receiver
76 DO I Read data input from the digital audio interface receiver
77 VCC — Power supply terminal (+3.3V)
78 BST2 O Boot strap control signal output to the audio digital signal processor 2
79 PM2 O PLL initialize signal output to the audio digital signal processor 2
80 XRST2 O System reset signal output to the audio digital signal processor 2 “L”: reset
81 HACN2 I Acknowledge signal input from the audio digital signal processor 2
82 HCS2 O Chip select signal output to the audio digital signal processor 2
83 GB9
I
Audio signal input from the audio digital signal processor 1
84 BST1
O
Boot strap signal output to the audio digital signal processor 1
85 HCS1
O
Chip select signal output to the audio digital signal processor 1
86 A1 IN
I
Sircs signal input for CONTROL A1 II
87 A1 OUT
O
Sircs signal output for CONTROL A1 II
88 HACN1
I
Acknowledge signal input from the audio digital signal processor 1
89 XRST1
O
System reset signal output to the audio digital signal processor 1 “L”: reset