11
4-7. IC BLOCK DIAGRAMS
• Tuner section
3
6
11
2
5
8
1
4
14
15
12
9
10
16
13
7
FM IF AMP
LIMITER
AF/NULL
METER
QUADRATURE
DET
AF AMP
IF OFF
NULL METER
SHORTING
LEVEL
DET
METER
DRIVE
MUTING
CIRCUIT
DETUNE
DET
GND
B+
1
2
3
4
REG
GND
CONTROL
REG
5
6
7
QUALITY BIT
GENERATOR
DEFFERENTIAL
DECODER
BIPHASE
SYMBOL
DECODER
OSCILLATOR
AND
DIVIDER
57kHz
BANDPASS
(8th ORDER)
CONTAS LOOP
VARIABLE AND
FIXED DIVIDER
REFERENCE
VOLTAGE
ANTI-
ALIASING
FILTER
CLOCKED
COMPARATOR
TEST LOGIC AND OUTPUT
SELECTOR SWITCH
RECONSTRUCTION
FILTER
14
15
16
13
12
11
10
9
3
2
1
4
5
6
7
8
CLOCK REGENERATION
AND SYNC
VP1
RDCL
TS7
OSCO
OSCI
V
DDD
V
SSD
TEST
TSTL
D
QUAL
RDDA
Vref
MUX
V
DDA
V
SSA
CIN
SCOUT
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7/23/2017
Digitized in Heiloo Netherland