Sony SS-HQ1, Application Notes

Page: 228 / 258

- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
222
12.2.12. V Reset H Reset Mode (VRHR)
V Reset H Reset Mode synchronizes the camera vertical, horizontal, and LALT (PAL) phases to the external
EXT-VD, EXT-HD, and EXT-LALT (PAL) reset signals.
The SGMODE setting is 5[h]. (See
Table 12.2-5
.)
System Configuration
The master signal is the external reset signal.
EXT-VD resets the vertical direction counter inside the CXD3172AR.
EXT-HD resets the horizontal direction counter inside the CXD3172AR.
EXT-LALT resets the LALT counter inside the CXD3172AR.
EXT-CLK, which is synchronized to the external reset signal, must be input to ECK (pin 88) or MCK (pin 43).
Note that the configuration in this case is different from that of the 1-clock digital encoder system or 2-clock
MCK-PLL system.
A block diagram of the 1-clock digital encoder system is shown in
Fig 12.2-36
. A block diagram of the 2-clock
MCK-PLL system is shown in
Fig 12.2-37
. The external input signal is presented in
Table 12.2-29
, and related
parameters are shown in
Table 12.2-30
.
Fig 12.2-36 V Reset H Reset Mode (1-clock digital encoding)
CXD3172AR
42
43
88 87 86
46
47
48
44
49
57 58
ESC
I
ESC
O
EC
K
PCO
M
P
E
XVIDE
O
Y
E
XVIDE
O
S0 S1
S4
S3
S2 MCK
3.3V
EXT-HD
EXT-VD
EXT-LALT
EXT-CLK