40
SPP-S2720
Pin No.
Pin Name
I/O
Description
58
FCSN0
O
Chip enable signal output to the flash memory “L” active
Not used (open)
59
GPIO1
O
Not used (open)
60
HCSN1
I
Chip select signal input from the system controller (IC301) “L” active
61
ALE
O
Address latch enable signal output to the flash memory
Not used (open)
62
CLE
O
Command latch enable signal output to the flash memory
Not used (open)
63
FCSN1
I/O
Not used (open)
64 to 66
GPIO6 to GPIO8
I/O
Not used (open)
67
MODEL
SELECT0
I
Model setting terminal (fixed at “L”)
68
MODEL
SELECT1
I
Model setting terminal (fixed at “L”)
69
(SCLK)
I
Serial data transfer clock signal input from the RF unit (RF271)
70
(FSYNC)
I
Sync signal input from the RF unit (RF271)
71
(DL0)
I
Receive data input terminal
72
(DL1)
O
Transmit data output terminal
73
GPIO15
I/O
Not used (open)
74
GND
—
Ground terminal
75
VCC
—
Power supply terminal (+5V)
76
DGPIO15
O
Not used (open)
77
DGPIO14
O
VCO control signal output
78 to 82
DGPIO13 to
DGPIO9
I/O
Not used (open)
83
DGPIO8
I/O
Not used (pull up)
84
DGPIO7
I/O
Not used (fixed at “L”)
85
DGPIO6
I/O
Not used (open)
86
DGPIO5
I/O
Not used (fixed at “L”)
87 to 91
DGPIO4 to
DGPIO0
I/O
Two-way data bus with the flash memory
Not used (open)
92
GND
—
Ground terminal
93
VCC
—
Power supply terminal (+5V)
94
DRDN
O
Read enable signal output to the flash memory “L” active
Not used (open)
95
DWRN
O
Write enable signal output to the flash memory “L” active
Not used (open)
96 to100
AGPIO0 to
AGPIO4
I/O
Not used (open)
Summary of Contents for SPP-S2720
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