5-1
SECTION 5
INTERF
A
CE,
IC PIN FUNCTION DESCRIPTION
SL
V
-ED1/ED4/ED7/ED8
TAPE
TAPE
PB •
REC •
Signal
Pin No.
I/O
STOP
FF
REW
THREAD-
UNTHREAD-
PB
PAUSE
SLOW
×
2
CUE
REVIEW
REC
PAUSE
ING
ING
CAP QR
MA-323
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
*
2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IC161
(¢
DRM PG
MA-323
I
*
3
*
1
*
1
*
4
*
4
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
IC161
#ª
DRM FG
MA-323
I
*
3
*
6
*
6
*
4
*
4
*
6
*
6
*
6
*
6
*
6
*
6
*
6
*
6
IC161
#•
CAP FG
MA-323
I
H/L
*
5
*
5
*
4
*
4
*
5
H/L
*
5
*
5
*
5
*
5
*
5
H/L
IC161
$º
CAP VS
MA-323
O
*
7
*
7
*
7
*
7
*
7
*
8
*
7
*
7
*
8
*
8
*
8
*
8
*
7
IC161
@∞
DRM VS
MA-323
O
*
9
*
9
*
9
*
9
*
9
*
9
*
9
*
9
*
9
*
9
*
9
*
9
*
9
IC161
@§
5-2. SYSTEM CONTROL – SERVO PERIPHERAL CIRCUIT INTERFACE (MA-323 BOARD IC161)
∗
1.
30 Hz pulse.
∗
2.
Pulse at tape running.
∗
3.
“L” when drum rotation stop.
∗
4.
Unstable period pulse.
∗
5.
Pulse of period in proportion to tape speed.
∗
6.
360 Hz pulse.
∗
7.
Pulse at tape running.
∗
8.
Approx. 2 msec period “H” or “L” pulse.
∗
9.
Approx. 1.5 msec period “H” or “L” pulse.
STOP/
TAPE
TAPE
REC •
REC •
Signal
Pin No.
I/O
FF/
THREAD-
UNTHREAD-
PB
PAUSE
SLOW
×
2
CUE
REVIEW
REC
PAUSE
REW
ING
ING
RF SWP
MA-323
O
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
(SW30)
IC161
@¢
QVD
MA-323
O
L
L
L
*
2
*
3
*
3
*
3
*
3
*
3
L
L
IC161
@¶
C SYNC
MA-323
I
*
4
*
4
*
4
*
4
*
4
*
4
*
4
*
4
*
4
*
4
*
4
IC161
%¢
5-1. SYSTEM CONTROL – VIDEO BLOCK INTERFACE (MA-323 BOARD IC161)
∗
1.
30 Hz pulse with 50% duty cycle. Synchronized with rotation of drum.
∗
2.
Normal PB “L”. V period “H” pulse when
×
1.
∗
3.
V period “H” pulse.
∗
4.
Composite Sync signal (positive polarity).
Summary of Contents for SLV-ED1PL
Page 6: ...1 2 ...
Page 7: ...1 3 ...
Page 8: ...1 4 ...
Page 9: ...1 5 ...
Page 10: ...1 6 ...
Page 11: ...1 7 ...
Page 12: ...1 8 ...
Page 13: ...1 9 ...
Page 14: ...1 10 1 10 E ...
Page 19: ...SLV ED1 ED4 ED7 ED8 3 1 3 2 SECTION 3 BLOCK DIAGRAM 3 1 OVERALL BLOCK DIAGRAM ...
Page 23: ...SLV ED1 ED4 ED7 ED8 3 10 3 9 3 5 AUDIO BLOCK DIAGRAM ...
Page 24: ...SLV ED1 ED4 ED7 ED8 3 12 3 6 TUNER BLOCK DIAGRAM 3 11 740m Vp p 24 576 MHz IC1 REC PB ...
Page 25: ...SLV ED1 ED4 ED7 ED8 3 14 3 13 3 7 MODE CONTROL BLOCK DIAGRAM ...
Page 26: ...SLV ED1 ED4 ED7 ED8 3 16 E 3 8 POWER BLOCK DIAGRAM 3 15 ...
Page 28: ...SLV ED1 ED4 ED7 ED8 4 3 4 4 4 1 FRAME SCHEMATIC DIAGRAM FRAME ...
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