5-10
RM-B150
IC
TC74HC4053AFS (TOSHIBA)FLAT PACKAGE
TC74HC4053AFS-EL
0
0
0
0
0
0
0
0
1
CONTROL INPUTS
12
13
2
1
5
3
X0
X1
Y0
Y1
Z0
Z1
6
EN
X
Y
Z
14
15
4
V
EE
*
7
V
EE
C
0
0
0
0
1
1
1
1
x
B
0
0
1
1
0
0
1
1
x
Y1
I/O
Y0
I/O
Z1
I/O
Z
I/O
Z0
I/O
EN
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y
I/O
X
I/O
X1
I/O
X0
I/O
A
IN
B
IN
C
IN
GND
V
DD
V
EE
*
OPEN
A
11
OPEN
B
10
OPEN
C
9
A
0
1
0
1
0
1
0
1
x
SELECT
EN
ON CHANNEL
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
X0
X1
X0
X1
OPEN
:
V
DD
_
V
EE
=
+
3 V to
+
12 V
V
EE
<
GND
0
1
x
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
C-MOS TRIPLE 2-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
—TOP VIEW—
TC74VHC238FS(EL) (TOSHIBA)FLAT PACKAGE
A
IN
B
IN
C
IN
EN1
IN
EN2
IN
EN3
IN
Y7
OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y0
OUT
Y1
OUT
Y2
OUT
Y3
OUT
Y4
OUT
Y5
OUT
Y6
OUT
GND
V
DD
A
B
C
EN
1
2
3
15
14
13
12
11
10
9
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
EN
0
1
1
1
1
1
1
1
1
INPUT
OUTPUT
4
5
6
EN1
EN2
EN3
Y7
0
0
0
0
0
0
0
0
1
Y6
0
0
0
0
0
0
0
1
0
Y5
0
0
0
0
0
0
1
0
0
Y4
0
0
0
0
0
1
0
0
0
Y3
0
0
0
0
1
0
0
0
0
Y2
0
0
0
1
0
0
0
0
0
Y1
0
0
1
0
0
0
0
0
0
Y0
0
1
0
0
0
0
0
0
0
EN =
EN1
•
EN2
• EN3
C
x
0
0
0
0
1
1
1
1
B
x
0
0
1
1
0
0
1
1
A
x
0
1
0
1
0
1
0
1
C-MOS 3-TO-8 LINE DECODER/DEMULTIPLEXER
—TOP VIEW—
0
1
x
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
TC7W00FU (TOSHIBA)CHIP PACKAGE
TC7W00FU(TE12R)
1
2
3
GND 4
8 V
DD
7
6
5
1
2
7 Y =
3
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
0
0
1
: LOW LEVEL
: HIGH LEVEL
A
B
Y
Y = A • B =
A
+
B
A
B
5
6
C-MOS DUAL 2-INPUT NAND GATE
—TOP VIEW—
TC7W04FU(TE12R) (TOSHIBA)FLAT PACKAGE
TC7W08FU (TOSHIBA)CHIP PACKAGE
TC7W08FU(TE12R)
TC7W14FU(TE12R) (TOSHIBA)CHIP PACKAGE
TC7WU04FU(TE12R) (TOSHIBA)CHIP PACKAGE
1
2
3
8 V
DD
6
7
GND 4
5
A
A
Y =
1
7
Y
A
0
1
Y
1
0
0 : LOW LEVEL
1 : HIGH LEVEL
Y =
A
3
5
6
2
C-MOS HEX INVERTERS
—TOP VIEW—
1
2
3
8 V
DD
6
7
GND 4
5
A
B
A
B
Y =
1
2
7
Y
A
0
0
1
1
Y
0
0
0
1
B
0
1
0
1
0 : LOW LEVEL
1 : HIGH LEVEL
Y = A • B =
A
+
B
3
5
6
C-MOS 2-INPUT AND GATE
—TOP VIEW—
1
2
3
GND 4
8 V
DD
7
6
5
1
A
7
Y
3
5
A
0
1
Y
1
0
0
1
: LOW LEVEL
: HIGH LEVEL
A
Y
6
2
Y =
A
C-MOS HEX INVERTERS
—TOP VIEW—
Y = A
A
Y
Y =
A
1
3
6
7
5
2
0 : LOW LEVEL
1 : HIGH LEVEL
8
7
6
5
1
2
3
4
Y
1
0
A
0
1
C-MOS HEX INVERTERS
—TOP VIEW—