– 80 –
Pin No.
Pin Name
I/O
Function
44
TST4
I
Test pin (Fixed at “L” level.)
45
PDO
O
RX-PLL phase comparator output
46
SELC
I
Oscillation frequency select signal input (Fixed at “L” level in this set.)
47
MUTA
I
Mute input. “H” to mute, and REC monitor sound is also muted.
48
PLCO
I
RX-PLL’s external VCO clock input (512fs reference)
49
PLVR
O
Output of phase comparator signal for RX-PLL. (2fs generated from PLL clock.)
(Not used in this set.)
50
PLRF
O
Output of phase comparator signal for RX-PLL. (RX SYNC detect signal 2fs)
(Not used in this set.)
51
MSSL
I
Master mode/slave mode slelect. “H” for master mode. (Fixed at “H” level in this set.)
52
RX
I
Digital interface signal input
53
VDD
—
+5V
54
TX
O
Digital interface signal output
55
SELA
I
Test pin (Fixed at “L” level.)
56
EXSY
I/O
External sync signal input/output
57
EXSN
I/O
External sync signal input/output
58
F128
I/O
128fs signal/256fs signal (high speed) input/output
59
F256
O
256fs signal/512fs signal (high speed) output (Not used in this set.)
60
F512
O
512fs signal output (Not used in this set.)
61
ADLF
I
ADDT, ADDI, ADDN serial data LSB/MSB first select input. “L” for LSB first.
62
DALF
I
DADT, DADO serial data LSB/MSB first select input. “L” for LSB first.
63
XT2O
O
X’tal oscillation circuit 2 output. (Not used in this set.)
64
XT2I
I
X’tal oscillation circuit 2 input
65
VSS
—
Ground
66
XT3O
O
X’tal oscillation circuit 3 output
67
XT3I
I
X’tal oscillation circuit 3 input
68
FSEN
I
F128, BCK, LRCK input/output select input. “H” for output.
69
LR03
O
Inverted LR02 signal (Not used in this set.)
70
LR02
O
Control byte (1). Bit 1: 16BCK delayed LRCK signal when “L” and LRCK clock output by
RX-PLL when “H” (Not used in this set.)
71
LR01
O
15BCK delayed LRCK signal
72
LRCK
I/O
fs/2fs (high speed) signal input/output
73
WCK
O
2fs/4fs (high speed) signal output (Not used in this set.)
64fs/128fs (high speed) signal input/output
AD serial data input
DA serial data output
DIGITAL IN audio data output
DIGITAL OUT Validity flag data input
DADT data’s interpolation data/descrimination signal output. “H” for interpolation data.
“H” output indicates that error correction status monitor data is being output to D7 to D0.
(Not used in this set.)
84
D7
I/O
External RAM data input/output (MSB)
85
D6
I/O
External RAM data input/output
86
D5
I/O
External RAM data input/output
87
D4
I/O
External RAM data input/output
88
D3
I/O
External RAM data input/output
89
D2
I/O
External RAM data input/output
90
VSS
—
Ground
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