Sony ICD-SX68 Marketing, Service Manual

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ICD-SX68/SX68DR9/SX78/SX78DR9/SX88
34
Pin No. Pin Name I/O Description
T2 SDR_CSZ1 O Chip select signal (Low active) (Not used (Open))
T3 SDR_CSZ0 O Chip select signal (Low active)
T4 SDR_BA1 O Bank address
T5 SDR_RASZ O RAS signal (Low active)
T8 SDR_CKE1 O Clock enable signal (Not used (Open))
T9 GND — GND
T10 MWI_SO O Data output (Not used (Open))
T17 U70_SOUT O Serial data output
T18 U70_SRIN I Serial data input
T19 GND — GND
T22 LCD_R5 O R data (Not used (Open))
T23 NC — Not used (Open)
T24 C_TMS I CPU debugger connection/On terminal
T25 VLOG O REGLOG power output terminal (1.86V)
T26 CKO O Crystal connection/On terminal
U1 SDR_A12 O SDR address output
U2 SDR_A11 O SDR address output
U3 SDR_A10 O SDR address output
U4 SDR_A9 O SDR address output
U5 SDR_A8 O SDR address output
U8 SDR_CASZ O CAS signal (Low active)
U9 GND — GND
U10 MWI_CS0 O Chip select 0 (Not used (Open))
U11 MWI_SK O Clock output (Not used (Open))
U12 GI/O_P1 I/O General purpose input/output terminal 1 (Not used (Open))
U13 GI/O_P0 I/O General purpose input/output terminal 0 (Not used (Open))
U14 L0_DET I Voltage monitor/reset of logic 0 block (Not used (Open))
U15 L1_DET I Voltage monitor of logic 1 block
U16 ERR_RST_REQZ O Not used (Open)
U17 CK32KI I Reference clock input 32.768 kHz (Not used (Open))
U18 REFCLKO O Reference clock output
U19 D_TCK O Input/output and interrupt input to general purpose I/O
U22 C_TDO O CPU debugger connection/On terminal
U23 VLOGIN I REGLOG power input terminal
U24 C_TCK I CPU debugger connection/On terminal
U25 VPLL O REGPLL power output terminal (1.2V)
U26 CKI I Crystal connection/On terminal
V1 I/O_A — Power supply to I/OA
V2 I/O_A — Power supply to I/OA
V3 I/O_A — Power supply to I/OA
V4 SDR_A6 O SDR address output
V5 SDR_A5 O SDR address output
V8 SDR_A7 O SDR address output
V9 GND — GND
V10 SPI1_SK O SPI1 clock output
V11 MWI_CS1 O Chip select 1 (Fixed to “L”)
V12 GND — GND
V13 GND — GND
V14 GND — GND
V15 GND — GND
V16 DSP_DET I Voltage monitor of DSP block
V17 D_TMS O CPU debugger connection/On terminal
V18 D_TDO I CPU debugger connection/On terminal (Not used (Open))
V19 D_TRSTZ I CPU debugger connection/On terminal (Not used (Open))
V22 C_RTCK O CPU debugger connection/On terminal
V23 C_TRSTZ I CPU debugger connection/On terminal (Low active)
V24 VPLLIN I REGPLL power input terminal
V25 VDSPIN I REGDSP power input terminal
V26 VDSP O REGDSP power output terminal (Not used (Open))
W1 I/OGND — GND