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61
1
2
3
4
6
VINL
VREF
VINR
VREF(N)
VREF(P)
SFOR
PWON
SYSCLK
5
15
14
10
9
DATAO
WS
FSEL
VSSA
VDDA
BCK
VSSD
VDDD
16
13
12
11
ADC
(Σ∆)
ADC
(Σ∆)
DECIMATION
FILTER
DIGITAL
INTERFACE
CLOCK
CONTROL
7
8
DC-CANCELLATION
FILTER
1
2
3
4
6
7
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15
16 17 18 19
20 21 22
44 43 42
41 40 39 38 37 36 35
34
RESET
RTCB
VDDD
PREEMO
NC
NC
NC
TEST2
WSO
SELSTATIC
TEST1
DATAO
VDDD(C)
VSSD
VSSD(C)
L3DATA
L3CLOCK
DATAI
BCKI
WSI
BCKO
VDDA(PLL)
MUTE
SELCHAN
NC
SPDIF0
VOUTL
SELCLK
SELSPDIF
LOCK
VOUTR
V
DDA(DAC)
SPDIF1
VSSA(PLL)
PREEM1
CLKOUT
NC
VDDA
VSSA
VSSA(DAC)
VREF
TC
L3MODE
NC
L3
INTERFACE
DATA
OUTPUT
INTERFACE
IEC 958
DECODER
AUDIO FEATURE PROCESSOR
INTERPOLATOR
NOISE SHAPER
DAC
DAC
DATA
INPUT
INTERFACE
CLOCK
AND
TIMING CIRCUIT
5
8
9
10
Summary of Contents for HMC-NX5MD
Page 44: ...44 44 HMC NX5MD 6 3 SCHEMATIC DIAGRAM CD SECTION Page 50 PIN FUNCTION ...
Page 47: ...47 47 HMC NX5MD 6 6 SCHEMATIC DIAGRAM MD SECTION 1 2 48 48 48 PIN FUNCTION ...
Page 48: ...48 48 HMC NX5MD 6 7 SCHEMATIC DIAGRAM MD SECTION 2 2 47 47 47 52 52 PIN FUNCTION ...
Page 49: ...49 49 HMC NX5MD 6 8 SCHEMATIC DIAGRAM MAIN SECTION 1 2 Page 52 Page 50 Page 50 ...
Page 52: ...52 52 HMC NX5MD 6 11 SCHEMATIC DIAGRAM DIGITAL SECTION Page 48 Page 48 Page 49 PIN FUNCTION ...
Page 54: ...54 54 HMC NX5MD 6 13 SCHEMATIC DIAGRAM PANEL SECTION Page 50 ...