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58
HCD-VP800AV
• IC502 M30622MGA-A59FP (CD MECHANISM CONTROLLER) (VIDEO BOARD)
Pin No.
Pin Name
I/O
1
SENSE
I
Internal state (SENSE) monitor input
2
SENSE CLK
O
Serial data reading clock output
3
RESOLUTION
O
Y resolution output
4
CROMA LEVEL
O
Chroma level controll signal output
5
DSP CLK
O
Serial data clock output
6
TSENS
I
Not used (open)
7
REMOTE IN
I
Not used (open)
8
BYTE
I
Not used (Connected to ground)
9
CNVSS
–
Ground
10
DSP MUTE
O
Muting on/off control signal output “H” : muting on
11
CTRL1 (L : DOUBLE)
O
Clock selection signal output (IC101) “L” : double speed (16.9344MHz)
12
XRESET
I
System reset input “L” : reset
13
XOUT
O
Main clock output terminal (10MHz)
14
VSS
–
Ground
15
XIN
I
Main clock input terminal (10MHz)
16
VCC
I
Power supply (+5V )
17
NMI
I
Not used (Connected to +5V)
18
SCOR
I
Subcode sync input
19
D SENS
I
Not used (open)
20
CL680 INT
I
Video CD interruption input
21
H. SYNC IN
I
H. sync signal input
22
BGP
O
Burst gate pulse signal output
23
—
I
Not used (open)
24
PWM3 (BD)
O
PWM3 signal output
25
—
I
Not used (open)
26
PWM2 (BD)
O
PWM2 signal output
27
—
I
Not used (open)
28
PWM1 (BD)
O
PWM1 signal output
29
I2C. CLK
I
IIC clock input from master control
30
I2C. DATA
I
IIC data input from master control
31
DATA1O
O
Serial data output to the FLASH writer
32
DATA1I
I
Serial data input from the FLASH writer
33
CLK1
O
Serial data transfer signal output the FLASH writer
34
RTS1
O
RTS (BUSY) signal to the FLASH writer
35
DATAO
O
Serial data output to MPEG decoder
36
DATA1
I
Serial data input from MPEG decoder
37
CLK1
O
Serial clock output to MPEG decoder
38
P. ON
I
Not used (open)
39
BUS XRDY
I
Not used (connected to +5V)
40
BUS
I
Not used (open)
41
BUS XHOLD
I
Hold signal input terminal from the FLASH writer
42, 43
BUS
I
Not used (open)
44
BUS XRD
I
Not used
45
V. SYNC
I
V sync signal input
46
BUS XWRL
O
Bus write signal output to the FLASH writer
47
LO. BOOST
I
Not used (open)
48
AUDIO MUTE
O
Not used (open)
49
LOAD OUT
I
Not used (open)
50
LOAD IN
I
Not used (open)
Discription