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42
HCD-GX250
Pin No.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
89
90
91
92
93
94
95
96
97
I/O
O
—
O
I
—
I
I
I
I
O
—
O
O
—
O
I
—
O
I
I
—
—
O
I
—
—
O
O
—
—
O
O
I
O
I
I
I
I
—
I
Pin Name
PCO
AVDD5
DDVROUT
DDVRSEN
AVSS5
DDCR
BCKI
PCMDI
LRCKl
LRCK
VSS
PCMD
BCK
VDD
EMPH
EMPHI
IOVDD2
DOUT
TEST
TES1
IOVss2
XVSS
XTAO
XTAI
XVDD
AVDD1
AOUT1
VREFL
AVSS1
AVSS2
VREFR
SQSO
SQCK
SBSO
EXCK
XRST
SYSM
D ATA
VSS
XLAT
Description
Master PLL charge pump output
Analog power supply
DC/DC converter output
DC/DC converter output voltage monitor pin
Analog ground
DC/DC converter reset pin
D/A interface bit clock input
D/A interface serial data input (2’s COMP, MSB first)
D/A interface LR clock input
D/A interface LR clock output f = Fs
Internal digital ground
D/A interface serial data output (2’s COMP, MSB first)
D/A interface bit clock output
Internal digital power supply
High when the playback disc has emphasis, low it has not
High when de-emphasis is ON, low when input OFF
I/O digital power supply
Digital Out output
Test pin Normally ground
Test pin Normally ground
I/O digital ground
Master clock ground
Crystal oscillation circuit output
Crystal oscillation circuit input
Master clock power supply
Analog power supply
Lch analog output
Lch reference voltage
Analog ground
Analog ground
Rch reference voltage
Analog power supply
I/O digital power supply
Rch “0” detection flag (Not used)
Lch “0” detection flag (Not used)
Crystal selection input (Not used)
Self-oscillation when high, oscillation stop when low
Subcode Q 80-bit and PCM peak and level data output
CD TEXT data output
SQSO readout clock input
Subcode P to W serial output
SBSO readout clock input
System reset Reset when low
Mute input Muted when high
Serial data input from CPU
Internal digital ground
Latch input from CPU The serial data is latched at the falling edge
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9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299