![background image](http://html.mh-extra.com/html/sony/hcd-ep505/hcd-ep505_service-manual_420653035.webp)
35
HCD-EP505
Pin No.
Pin Name
I/O
Description
78
VSS
—
Ground terminal
79
X2
O
Main system clock output terminal (4.194304 MHz)
80
X1
I
Main system clock input terminal (4.194304 MHz)
81
VDD
—
Power supply terminal
82
XT1
I
Sub system clock input terminal (32.768 kHz) Not used
83
XT2
O
Sub system clock output terminal (32.768 kHz) Not used
84
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
85
REMOTE
I
Remote control signal input from the remote control receiver
86
PWRFAIL
I
Power failure detection signal input terminal “L”: power failure, “H”: power on
87
RDSCLK
I
Serial data transfer clock signal input from the RDS decoder
(Used for the AEP, UK models)
88
CDCLK
I
Serial data transfer clock signal input from the CD block
89
SENSORB
I
Tape sensor input terminal Not used
90
SENSORA
I
Tape play/rec detect sensor input terminal “L” input when the tape play/rec detect
91
CD DOOR SW
I
CD lid open/close detect switch (SW300) input terminal “L”: CD lid is closed
92
CD-EN
O
CD power on/off control signal output terminal
93
SOL
O
Trigger plunger drive signal output terminal “H”: trigger plunger on
94
TU-EN
O
Tuner power on/off control signal output terminal
95
MOTOR-ON
O
Motor control signal output terminal
96
AMS
I
Whether a music is present or not from AMS is detected at auto music sensor
“L”: music is not present, “H”: music is present
97
ENCODERA
I
Jog dial pulse input from the rotary encoder (VOLUME) (A phase input)
98
ENCODERB
I
Jog dial pulse input from the rotary encoder (VOLUME) (B phase input)
99
AVSS
—
Ground terminal
100
KEY1
I
Key input terminal (A/D input)
Ver 1.1
Summary of Contents for HCD-EP505
Page 14: ...14 HCD EP505 MEMO ...