HCD-101
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
—
O
O
O
O
O
O
O
O
I
O
I
—
O
I
—
O
O
I
O
O
O
—
I
—
I
I
I
I
I
I
I
I
—
—
I
I
I
I
—
I
—
I
I
I
—
O
O
O
O
Description
Power supply (+5V)
AU_BUS output
Tuner pack (TB401) serial data output
Tuner pack (TB401) clock output
Tuner pack (TB401) latch output
Data output to electronic VOL (IC424) serial-to-parallel conversion IC (IC410)
Clock output to electronic VOL (IC424) serial-to-parallel conversion IC (IC410)
Latch output to serial-to-parallel conversion IC (IC410)
Latch output to electronic VOL (IC424)
SYSTEM RESET
Main clock oscillator output (5MHz)
Main clock oscillator input (5MHz)
Connected to Vss
Watch oscillator output (32.768 kHz)
Watch oscillator input (32.768 kHz)
Positive power supply (+5V)
CD clock output
CD data output
CD DSP sense input
CD DSP latch output
CD D/A latch output
CD Sub Q clock output
(Not used)
Sub Q data input
Ground
CDM chucking sensor
CDM disc sensor
CDM disc sensor
CDM disc sensor
CDM disc sensor
Identification input of destination
Key input
Key input
Built-in A/D converter analog power supply (+5V)
Built-in A/D converter reference voltage input (+5V)
DSP SCOR input
DSP clock input
AC power off detection
AU_BUS input
Ground
SIRCS remote control input
(Not used)
Tuner pack (TB401) TUNED input
Tuner pack (TB401) STEREO input
Tuner pack (TB401) DATA input
Positive power supply (+5V)
TA mute output
CDM 50 load output
CDM 50 load input
Tuner pack (TB401) mute output
Pin Name
D+5V
AUB OUT
ST DATA OUT
ST CLOCK
ST LATCH
TA DATA OUT
TA CLOCK
LATCH (S.P)
LATCH (VOL)
RESET
X2
X1
D.GND
XT2
XT1
D+5V
CD CLOCK
CD DATA
SENSE
DSP LATCH
DF LATCH
SQCLK
(OPEN)
SUBQ
AD.GND
DISC SET
DISC DET
LOAD END
DISC IN
DISC 8/12
DEST
KEY0
KEY 1
AD+5V
AD+5V REF
SCOR
RDS.CLOCK
AC.CUT
AUB IN
D.GND
SIRCS
RDS.DATA
TUNED
STEREO
ST DATA
D+5V
TA.MUTE
LOAD OUT
LOAD IN
ST.MUTE
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Description
CD PLAY LED output
CD PAUSE LED output
FL tube segment output
FIP controller pull-down resistor is connected here (–27V)
FL tube segment output
FL tube grid output
Pin Name
PLAY LED
PAUSE LED
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
VG–27V
S8
S7
S6
S5
S4
S3
S2
S1
S0
T11
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
5-13. IC PIN FUNCTION
• IC701 µPD780206GF-023-3BA
5-14. IC BLOCK DIAGRAMS
— 42 —
— 43 —
— 44 —
IC 102
BA6397FP
1
2
3
4
7
8
9
10
11
12
13
14
28
27
26
24
22
21
20
19
18
17
DRIVE
BUFFER
DRIVE
BUFFER
LEVEL
SHIFT
LEVEL
SHIFT
THERMAL
SHUT DOWN
REGULATOR
DRIVER MUTE
LEVEL
SHIFT
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
LEVEL
SHIFT
DRIVE
BUFFER
DRIVE
BUFFER
15
16
23
25
5
6
OUT1A
OUT1B
IN1A
IN1B
TR-B
REG 0
XRST
GND
IN2A
IN2B
OUT2A
OUT2B
GND
OP-OUT
GND
OUT4A
OUT4B
IN4A
IN4B
VC
V
CC
V
CC
V
CC
V
CC
IN3B
IN3A
OUT3B
OUT3A
OP+
OP–
IC103
CXD2507AQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21 22 23 24 25 26 27 28 29 30 31 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
58
60
61
62
63
64
DIGITAL
CLV
D/A
INTERFACE
16K
RAM
ERROR
CORRECTOR
CLOCK
GENERA
T
O
R
3
6
3
5
14
4
5
57 56 55 54
59
SERVO AUTO
SEQUENCER
DIGITAL
PLL
EFM
DEMODULATOR
CPU
INTERFACE
SUB CODE
PROCESSOR
ASYMMETRY
CORRECTOR
DIGITAL
OUT
FOK
MON
MDP
MDS
LOCK
TEST
FILO
FILI
PCO
VSS
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
WDCK
DATA
XRST
SENS
MUTE
SQCK
SQSO
EXCK
SBSO
SCOR
VSS
WFCK
EMPH
DOUT
C4M
FSTT
XTSL
XTAO
XTAI
MNTO
XLON
SPOD
SPOC
SPOB
SPO
A
CLK
O
VDD
XL
T
O
DA
TO
CNIN
SEIN
CLOK
XLA
T
LRCK
PCMD
BCLK
GT
OP
XUGF
XPCK
VDD
GFS
RFCK
CZPO
XR
OF
MNT3
MNT1
IC105
LB1638M
1
2
3
4
5
6
7
8
9
10
GND
IN1
VCC
IN2
GND
N.C.
OUT2
VS
OUT1
N.C.
CONTROL LOGIC
