5-1
EA-80
SECTION 5
BLOCK DIAGRAM
1. Communication
In case LLC-8000 sends data “0”
The LLC-8000 turns the voltage at the D.SIG terminal(pin 4 of CN1) on the AU-254 board to 0 V.
It then turns the voltage at the pin 1 of the CPU(IC1) on the SW-952 board to 0.5 V, and the CPU recognizes data as “0”.
In case EA-80 sends data “0”
The EA-80 turns the voltage at the pin 3 of the CPU(IC1) on the SW-952 board to 0 V.
When the voltage at the pin 3 of the CPU is 0 V, the parts, R13, 17 and 18 on the SW-952 board, and also Ra and Rb on the
LLC-8000, turn the voltage at the D.SIG terminal(pin 4 of CN1) on the AU-254 board to 0.5 V. The RxD terminal on the
LLC-8000 recognizes data as “0” because the D.SIG terminal becomes 0.5 V.
2. Audio
The audio input and output levels are shown below. The VOLUME, control knob (RV1) on the SW-952 board adjusts
a sound level from
-
8 dB to
+
8 dB. (The RV1 cannot control AUX L IN and AUX R IN signals.)
OUTPUT
HS-PHONE(L)
HS-PHONE(R)
MONI
PGM
MIC
INPUT (LEVEL)
PGM -10 dB
-
19 dB
-
19 dB
X
-
10 dB
X
Turning Q1 on makes sound mute.
INCOM -10 dB
-
19 dB
-
19 dB
X
X
X
HS-MIC -54 dB
-
19 dB
-
19 dB
-
10 dB
X
-
10 dB
Turning Q2 on makes sound mute.
AUX L -10 dB
-
19 dB
X
-
16 dB
X
X
AUX R -10 dB
X
-
19 dB
-
16 dB
X
X
Level allowance:
±
3 dB
X: No output
Frequency response: 50 through 10 kHz;
+
3/
-
10 dB
AUX L IN
CN3-1
AUX R IN
CN3-2
A.GND
CN1-2
COLD
CN1-6
D.SIG
CN1-4
P.GND
CN1-1
PGM
CN1-3
INCOM
CN1-8
MONI
CN1-5
PGM OUT CN3-4
MIC OUT
CN3-5
HS-MIC
J1-1
HS-PHONE(L)
J2-1
HS-PHONE(R)
J2-2
EA-80
LLC-8000
[-10dB]
[-10dB]
{-54dB}
{-20dB}
[-20dB]
(-19.5dB)
<-18.5dB>
(-36.5dB)
<-35.5dB>
{-37dB}
(-10dB)
{-11dB}
S-MIC SW
PGM-MONI SW
5V
IC1
R18
R13
R17
3
1
RXD
TXD
D1~6
SW1~6
VOLUME
Q1
RV1
R
a
R
b
Q2
MONI
PGM
INCOM
+15V
5V
5V
TXD
RXD
{-10.5dB}
[-17dB]
(-10dB)
<-10dB>
+15V
CN1-7
(-11dB)
<-10dB>
{-11.5dB}
1
2
3
1
2
3
SW-952 BOARD
0dB=0.775Vrms SIGNAL:1KHz VOLUME:CENTER
