Sony CXD5602, User Manual

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CXD5602 User Manual
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3.5.3.3 SYSPLL Block Setting Confirmation
The frequencies of SYSPLL can be confirmed by the XOSC frequency and division ratio setting register as shown
in Table Clock and Reset (Clock Reset Generator)-53.
Table Clock and Reset (Clock Reset Generator)-53 SYSPLL Frequency Confirmation
XOSC
Frequency
[MHz]
SYS_PLL_CTRL2.ISP_L
V_SELRCDIV[1:0]
SYS_PLL_CTRL2.ISP_L
V_SELFBDIV[2:0]
SYSPLL
Frequency
[MHz]
16.368 0 0 163.68
0 1 196.42
19.2 1 2 144.00
0 0 192.00
26 1 1 156.00
1 2 195.00
32.736 1 0 163.68
1 1 196.42
52 3 1 156.00
3 2 195.00
3.5.3.3.1 Register Descriptions
Table Clock and Reset (Clock Reset Generator)-54 shows the control registers related to the SYSPLL block.
Table Clock and Reset (Clock Reset Generator)-54 SYSPLL Block Status Registers
Address Register
Name
Bit Field
Name
Type Bit Initial
Value
Description
0x04100588 SYS_PLL
_CTRL1
Reserved RW [31:4] 0 Reserved
ISP_LV_ENDSPCLK RW [3] 0
Indicated as ANA(7) in
Figure Clock and
Reset (Clock Reset Generator)-34
Clock Enable for each function block
0: Clock supplied, 1: Clock stopped
Reserved RW [2] 0 Reserved
ISP_LV_ENGPADC
CLK
RW [1] 0
Indicated as ANA(6) in
Figure Clock and
Reset (Clock Reset Generator)-34
Clock Enable for GNSS
0: Clock supplied, 1: Clock stopped
Reserved RW [0] 0 Reserved
0x0410058C SYS_PLL ISP_LV_SELRCDIV RW [31:30] 0 RCDIV frequency division ratio switching