Sony CXD2701Q Data Book Download

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Summary of Contents for CXD2701Q

Page 1: ...IB 2 Semiconductor IC ...

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Page 3: ...Semiconductor Integrated Circuit Data Book 1992 List of Model Names Index by Usage Description Digital Filter 1C A D D A Converter ADSP Audio Digital Signal Processor Digital Audio Interface IC ...

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Page 5: ...Semiconductor Integrated Circuit Data Book 1992 SONY ...

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Page 7: ...rs of Sony products If however you are dissatisfied with this book in any way please write we welcome suggestions and comments Sony reserves the right to change products and specifications without prior notice Application circuits shown are typical examples illustrating the operation of the devices Sony cannot assume responsibility for any problems arising out of the use of these circuits or for a...

Page 8: ...s 5 Digital Audio ICs 6 Analog Audio ICs 7 Floppy Dish Hard Disk Drive ICs 8 Radio Communication System ICs 9 A D D A Converters 10 ECL Logic ASS P ICs 11 Microcomputers 12 Memories 13 Discrete Semiconductors 14 Laser Diodes In addition a List of Semiconductor Products covering all manufactured device on the market is issued twice a year Data books offer information pertaining to the listed produc...

Page 9: ...r IC Application 10 1 Absolute maximum ratings 10 2 Protection against electrostatic breakdown 11 3 Mounting method 15 5 Quality Assurance and Reliability 17 6 Data Sheets 23 1 Digital Filter IC 23 2 A D D A Converter 75 3 ADSP Audio Digital Signal Processor 105 4 Digital Audio interface IC 203 ...

Page 10: ...1 List of Model Names Type Page Type Page Type Page CXD1160AP AQ 107 CXD2552Q 77 CXD2560M 49 CXD1211P 205 CXD2554M P 38 CXD2561BM 85 CXD1244S 25 CXD2555Q 94 CXD2701Q 179 CXD1355AQ 159 CXD2557M 67 6 ...

Page 11: ...verter 77 CXD2561BM 1 bit D A converter 3rd order noise shaper 85 CXD2555Q 1 bit A D D A converter Built in digital filter 2nd order noise shaper 94 I 3 ADSP Audio Digital Signal Processor Type Fu notions Page CXD1160AP CXD1160A0 Software realized various digital audio data Double accuracv arithmetic possible 107 CXD1355AQ Programmable DSP and 8 is over sampling digital filter for surround 159 Pro...

Page 12: ... 20 22 MOS IC 5 7 23 79 Sony IC mark 2 New nomenclature Example C X A 1 1 A P Package mark P Plastic Dual In line Package D Ceramic Dual Inline Package M Small Outline LLeaded Package L Single In line Package Q Quad Flat L Leaded Package S Shrink Dual In line Package N Very Small Outline Package SSOP R Very Small Quad Flat Package Improvement mark A is affixed when specifications are improved Prod...

Page 13: ...age Reverse Mirror image pin out Improvement mark Improvement mark is affixed when specifications are partially improved Product number Identifies the individual product Product category mark K Memory Sony IC mark I 4 Microcomputer nomenclature Example CX P 5 06 8 QQOP Package mark P Q S OEM code Product number Indentifies the individual product Product category mark P Microcomputer Sony IC mark 5...

Page 14: ...ily Even if this temperature range is exceeded and some deterioration in operating charac teristics is noted the IC is not always damaged For some ICs the electrical characteristics at Ta 25 C are not guaranteed even in this temperature range 4 Storage temperature Tstg The temperature range for storing the IC which is not operating This temperature is restricted by the pack age material and the in...

Page 15: ...sing electrostatic generation in manufacture process A number of dielectric materials are used in manufacture process Friction of these mate rials with the substrate can generate static electricity which may destroy the semicon ductor device Factors that can cause electrostatic des truction in the manufacture process are shown below Causes of electrostatic destruction of semiconductor parts in man...

Page 16: ...g operation protective clothing for static electricity grounding mat ground strap cotton gloves Conductive gown X X 2 Grounding of operator s body The operator should connect the specified wrist strap to his arm example of grounding band cotton glove snap groundirig wire When using a copper wire for grounding connect a IMn resistance in series near the hand for safety 3 Handling of semiconductor d...

Page 17: ...Use conductive or antistatic treated plas tic IC magazines magazine conductive magazine 2 Bag Use a conductive bag to store ICs bag I conductive bag 3 Semiconductor device case Use a conductive case 4 Insertion of semiconductor device Insert the semiconductor device during the mounting process or on the belt conveyer The insertion should be done on a conductive sheet 5 Other points of caution Take...

Page 18: ...d rack work table for discharging 5 Handling of mounted substrates Wear cotton gloves when handling As far as possible avoid touching soldered faces When handling mounted substrates individu ally be sure to use a conductive bag Do not use a polyethylene bag handling of mounted substrate cotton glove conductive bag 2 Operation After inserting the semiconductor device into the substrate solder it as...

Page 19: ...nal is exposed at the cut off end the area for sol dering is restricted The portion near the resin is often covered with burrs when sealing with resin it is not in the soldering warranty area I warranty area for soldering device main body tie bar cut portion nw Resistance to soldering heat 1 Specification of JIS JIS specifies the method for testing the resistance to soldering heat This method is u...

Page 20: ...a solder pot the device moisture resistance may deteri orate and thermal stress generate cracks in the pallet Carefully observe the mounting conditions Recommended temperature profile when mounting infrared reflows is shown in the figure below 1 20 C 235 CnTa 10 see 3 to 4 C set 50 to 300 set preheated part reflow part time 16 ...

Page 21: ...ystem of qual ity assurance is firmly established From the early stages of research and development well into production sales and servicing orderly control is applied for the maintenance of high standards and further improvement Systematization and automation are pushed ahead to provide a stable output of high quality production In this respect the force in charge of im plementing the program is ...

Page 22: ...Quality assurance system of semiconductor products L IPQC In PrtCflSB Qua 14 y CaBttCl 2 Qai Quality Assurance Test 18 ...

Page 23: ...el Periodic Reliability Test Item Testing time LTPD Electrical Characteristics Test In order to know the initial quality level some types are selected and tested again Life Test high temperature operation high temperature and high humidity with bias pressure cooker up to LOOOh up to 1000 h up to 200 h 10 10 10 Environmental Test soldering heat resistance heat cycle 10s 100 cycles 15 15 Mechanical ...

Page 24: ... C 100c 10 Soldering heat resistance T solder 260 C 10s 10 Solderability T solder 230 C rosin type flux 5s 10 Mechanical shock X Y Z lS O00m s Haif part of sinusoidal wave of 0 5ms 3times for each direction 10 Vibration X Y G 200m s 10Hz to 2000Hz to 10Hz 4min Sinusoidal wave vibration 16minutes for each direction 10 Constant acceleration X Y 2 200 000m s 1 Centrifugal acceleration lminute for eac...

Page 25: ...ed Specification Development Planning Acceptance of Quality and Reliability I Trial Manufacturing Review Large Scale Trial Manufacturing Evaluation Acceptance of Quality and Reliability It Production Approval Production Shipping Function Characteristics Quality and Reliability Schedule Quantity and Cost Circuit Mask Wafer Process and Packaging I Characteristics Quality and Reliability Acceptance o...

Page 26: ...SZ1P SHRINK ZIG ZAG IN LINE PACKAGE p l ijfimm 70MIL Hg Zng in line Through Hole Lead 1 direction 8 1 Standard ilat package Q F P QUAD FLAT L LEADED PACKAGE P 1 p c 10mm D Bmm D 65mrn Gull Wing 4 direction SOP SMALL OUTLINE L LEAUED PACKAGE 00 p L27 nm SDMIL Gull Wing 2 di recti on Standard 2 direction chip carrier S J SMALL OUTLINE J LI ADED PACKAUK 0fa p 1 27 mm 50 MIL J l 2 directiors Shrink fl...

Page 27: ...Digital Filter IC ...

Page 28: ...ersions 4 8fs Filter length 213 16 18 bit output Attenuate deemphasis 25 CXD2554M For popular version 4 8fs Filter length 57 CXD2554P 16 18 bit output Attenuate deemphasis 38 CXD2560M Sfs Filter length 213 18 20 bit output Attenuate deemphasis 49 CXD2557M Audio data zero detection 67 24 ...

Page 29: ...e emphasis and a wide variety of built in functions Application Compact disc player Structure Silicon gate CMOS IC Package Outline Unit mm Absolute Maximum Ratings Ta 25 C Supply voltage Vdd 0 5 Input voltage Vi 0 5 Storage temperature Tstg 55 Allowable power dissipation Pd 40 pin SDIP Plastic 5 3 L uuuiiuuin l i r T HI SDIP 40P 12 I to 6 5 V to Vdd 0 5 V to 150 C 500 mW Ta 60 C Recommended Operat...

Page 30: ...MUTE Pin Configuration Top View GND T w Si TESTS testi 2 M TEST 7 ATT Z Z EST SHIFT s Z TESTS LATCH X Z EMP SOFT 6 Si NS INI T T 4 APT WS M C S 33 BCKO X IN GE m DATAL V i 51 END V z n GND BCK 1 M QATAR DATA Es is LRCKO LRCK E Z LE WS DPOL Ls Z 0l T16 te INAF 01 si CFST LFS E Z POL v 5 5 m MUTE NX Z z TEST4 TE5T2 20 S jj TEST 3 26 ...

Page 31: ... LFS 1 4Fs mode ON OFF available at H only during I S 18 SONY l2 S 1 Output format specified at L Sony at H l 2 S 19 NC 20 to 22 TEST 2 to 4 Test pin Normally fixed to L levei 23 MUTE Turns output to or offset value Active at H 24 DPOL Offset polarity L H 25 OFST Offset ON OFF Active at H 26 OUT16 18 Output data word length specified at 1 1 6 bit at H 1 8 bit 27 LEWS LE output Sony format WS outpu...

Page 32: ...ta hold time tlDH 20 ns Input LRCK set up time tJLRS 50 ns Input LRCK hold time tILRH 50 ns Output BCK pulse width twos Fx 1 6 9MHz Sony output mode 8Fs BCK24 CL 50pF 40 ns Output data set up time tODS 25 ns Output data hold time toon 25 ns Output BCK pulse width twOB Fx 16 9MHz l 2 S output mode 8Fs CL 50pF 60 ns Output data set up time tODS 35 ns Output data hold time tODH 35 ns Output BCK pulse...

Page 33: ...ONYs CXD1244S Timing Chart Input BCK DATA LRCK Output BCKO VooxC VooxC DATAO A 1Vou 2 j twia tlOS T Sh i Voo 2 twii _ tlLRS Vdo 2 twOB SdH tF tfi h Hy o T 7 W2 t QB tons toDH Vdo 2 fODS JL LRCKO Voo 2 29 ...

Page 34: ...Max Unit Shift pulse width Twisf 600 ns ATT set up time Tias 300 ns ATT hold time TlAH 600 ns Latch pulse width TwiLA 400 ns Latch set up time TlLAS 500 ns Schmitt input characteristics SHIFT LATCH Min Typ Max Unit Vt 0 54xVdo 3 3 0 76xVdd V Vt 0 24xVdd 2 0 0 43xVqc V 1 0 V U Oi 30 ...

Page 35: ...se shaping For respective outputs FIR 1 to 3 MR SOFT ATT figures are usually rounded off However by turning NS to H noise shaping can be applied NS register is cleared when I NIT is at L or NS at L 2 Soft muting By turning SOFT to HTl data can be smoothly muted or demuted Output amplitude 4 SOFT 3 Digital attenuator Can attenuate output data by means of transfer data from an external microcomputer...

Page 36: ...ppose that there are pieces of attenuator data ATT1 ATT2 and ATT3 and that ATT1 ATT3 ATT2 and that the place of attenuator data ATT1 is transferred first and ATT2 transferred next If ATT2 is transferred before The value of ATT2 is reached during the state of A in Fig l the attenuation directly approaches the value of ATT2 If ATT3 is transferred before the value of ATT2 is reached during the state ...

Page 37: ...ransferred 3 With INIT at 400 H is set as ATT data ATT 3 OOO i h POWER ON SOFT I The transition from ATT1 to ATT2 takes place in soft muting operation During attenuate operation SOFT is set to either ON or OFF it turns back to the original ATT data When ATT data 400 H Noise shaping is not applied regardless of NS ON or OFF When ATT data 400 H Noise shaping is applied regardless of NS ON or OFF 4 D...

Page 38: ... LRCK that is input has entered the window or not When the power supply is turned on should LRCK_ be out of the window the sync circuit stops the internal processing in timing with the center of the window Synchronously with the appearance of the next LRCKf the processing is started Through this operation synchronization between the exterior system and this LSI is established 2 Resynchronization b...

Page 39: ... will 8LRCK 24BCK DATAL DATAR APT LE H L no effect 4LRCK i 16BCK Staggered I DATA WS WS MIX data V t 10 I O signal latch timing 1 Input DPOL SOFT MUTE OFST OPOL 1N1T SONY I S LFS OUT16 18 MS EMP The above indicated input signals are latched by means of internal clocks equivalent to LRCK 2 Output LRCKO DATAL DATAR APT WS LEWS The above indicated output signals are iatched by means of internal clock...

Page 40: ...SONY CXD1244S r s o c E i g 3 UL 8 SQifc 8S e 36 ...

Page 41: ...Hz 20 0 0 Frequency characteristics s c io o is o Frequency KHz 0 0002 0 0001 m 8 o oooo i 00 Ripple characteristics i_ 5 0 10 0 15 0 Frequency KHz 20 0 Ripple characteristics 0 0001 0 0000 0 0001 _ s 1 1 5 0 10 15 0 Frequency KHz I Attenuate Attenuate 0 0 1 50 0 100 0 L ft All jjL Ji 0 0 44 1 a8 2 132 3 Frequency KHz 50 0 1C0 0 Lid I I I J Ut 3 S 2 176 4 364 6 352 6 Frequency KHz 37 ...

Page 42: ...t 2 s complement MSB first serial Output 2 s complement MSB first serial 16 or 18 bit slot selectable Applications Compact disc player Structure Silicon gate CMOS IC Absolute Maximum Ratings Ta 20 to 75X Supply voltage Vcc 0 5 to 6 5 Input voltage Vi 0 5 to Voo 0 5 Allowable power dissipation Pc 500 Storage temperature Tstg 55 to 150 CXD2554M 24 pin SOP Plastic CXD2554P 1 8 pin DIP Plastic 40 V v ...

Page 43: ...4M P CXD2554M Block Diagram I Pin Configuration test T 8f s 4tt i Xour d NC J V00 lNClfi BCKfi DATA QcT lrckQT wrffTz 24 SLOT 23 LRCKO 221 OATAL IT OATAR NO 2C jg vss 7a no 77 no sIbcko 7 ATT 7T SHIFT TJ LATCH 39 ...

Page 44: ...11TH FIR LATCH OFFSET P BUFFER RAM x h E D A I swrTC S e NOISE SHAPER I FRACTION NORMALIZE RAM FOR J3RDFIR RAM FOR IIR n v X Pin Configuration TEST T 8fs 4fs 7 xout x in T vdd T sckH DATA 7 lrck s I NIT a xj ji SLOT JtJlRCKO il DATAL ll DATAR 3 sslGNDI iDbcko ji ATT ii SHIFT o LATCH 40 ...

Page 45: ...T 1 Re synchronized by rising edge of this signal 10 13 LATCH 1 Latcti clock input 11 14 SHIFT 1 Shift clock input 12 15 ATT 1 Attenuate data input 13 16 BCKO o BCK output 14 19 Vss GND Powet supply C v 15 21 DATAR 4fs mode WCK output 8fs mode RCH serial data output 2 s complement 16 22 DATAL 4fs mode LCH and RCH time division serial data output 2 s complement 8fs mode LCH serial data output 2 s c...

Page 46: ...ced Vi Voo ov fx 16 9344 MHz 40 mA Note 1 TEST 8fs W BCK DATA LRCK MT LATCH SHIFT ATT SLOT Note 2 BCK DATA LRCK NTT LATCH SHIFT ATT AC characteristics Vdd 4 5 to 5 5 V Ta 20 to 75 C Item Symbol Condition Min Typ Max Unit Oscillation frequency input BCK frequency fx 10 16 9344 20 4 0 MHz Input BCK pulse width Input data set up time Input data hold time Input LRCK set up time Input LRCK hoid time tW...

Page 47: ...ut BCK DATA LRCK Audio output BCKO t DATA L DATA R LRCK O A tlDS A tWIB tlDK m 3 tODS low I Program input SHIFT X twlB XZZ3C tlLRS tlLBH 4 twOB tWOB m tso X r A A MSB 1st 10 t f tHOLO J JK 90 gov x tPR tt y o isr r LATCH LSB VlOtt 10n i 43 ...

Page 48: ...on The synchronizing circuit opens a window for six internal system clocks CK2 fx 4 to monitor whether the differentiated signal of the rise of LRCK LRCKf that may be input exists in it If the LRCK f is out of the window when the power supply is turned on the synchronizing circuit holds the CK2 at the time it is in the center of the window and lets it start as soon as the next LRCK f arrives This ...

Page 49: ...s carried on from the value at the time B or C to approach the value of ATT3 Transition from one piece of attenuator data to another is the same as in the case of soft muting Fig 1 Transition from one attenuator value to another E Input data timing I ATT Xi XeHXo X XD XD9XcwX07 irLTirjiTLnnj uATCH IT Fig 2 Timing of ATT SHIFT and LATCH ATT data is configured on the LSB first basis ATT data D Digit...

Page 50: ...NPUT DATA LRCK d s sc 3 0 s s c 3 c T 1 fs 4fs mode outputs BAT JMMk 16 bit slot mode 1 B bit slot mode 33 0 S 0 JMI0Mi MMM3 i3S G E SSi DATAR WCKO a UtCKO mnnjiATinnnnn T t 4f s 8fs mode ouipul DATAL 16 bit slot mode 18 bit slot mode D5 S L WMMMMMm jMMM immim JMMd MMMMMM Mzm immmm m j m 33m MM L j9 0 8S 80 Sl DATAR P 3 1 6 bit slot mode 18 bit slot mode b nmmm mmpmm f i mmmMpmmRfm bo o TJL r ATfi...

Page 51: ... Characteristics Quadrupled oversampling mode Frequency Characteristics 1 Pass band RESPONSE dB Frequency Characteristics 2 Stop band RESPONSE MB 0 400 o coo 0 400 0 800 1 200 25 0 0 0 5 0 tO O 15 0 20 0 FREQUENCY KHil 100 0 150 0 200 0 FREQUENCY KHi Octupled oversampling mode Frequency Characteristics 1 Pass band Frequency Characteristics 2 Stop band RESPONSE MB RESPONSE MB 0 400 o ooo 0 400 0 80...

Page 52: ... 3 H 1 1 11 hwwumhi 1 0 3 5 w 12 7 al Z 02 10 i i 0 1 0 3 vent Hole asiU hnnnnmnnnnnrf CXD2554P 18 pin DIP Plastic 300 mil Z2 i SONY NAME SOP 24P L101 ESA0 NAME SOP324 P 045Q AU JECEC CODE E 1 2 5 4 4 0 2 5 Lmnrmnnoni TirTTuinpnt 0 5 V II 0 15 SOUY SAVE QIP 1 8 P 1 1 EIAJ SAME DIPQ1H P 0300 AU JEDEC COOE 48 ...

Page 53: ...Noise shaper attenuator sort muting and de emphasis functions I O format Input 2 s complement MSB LSB first serial 16 bit or 18 bit slot selectable Output 2 s complement MSB LSB first serial 18 bit or 20 bit slot selectable Applications CD DAT BS tuner and digital amplifiers Structure Siiicon gate CMOS IC Absolute Maximum Ratings Ta 25 C Supply voltage Vod 0 3 to 7 0 Input voltage VI Allowable pow...

Page 54: ...k input CTL H FS48 input 6 CTL Fixed internally at L level H direct input mode L serial transfer mode 7 INtT Re synchronized by rising edge of this signal 8 BCKI BCK input 9 DATAI Data input 10 LRCKI 1 LRCK input 11 TEST 1 Test pin Fixed at L level in normal operation mode 12 Vss Power supply OV 13 128 Fs 1 28 Fs clock output 14 INVI 1 Inverter input 15 INVO Inverter output INVi 16 INV02 Inverter ...

Page 55: ...ol All outputs lo 2mA 0 4 Power supply current Ice 60 niA AC Characteristics Vdd 4 75 to 5 25V Ta 20 to 75 X GND 0V Item Symbol Condition Min Typ Max Unit Master clock input frequency Imclk 15 27 MHz Master CK pulse width tWMK 18 5 ns BCKI frequency facKi 3 5 MHz BCKI pulse width tWBI 100 ns DATAI set up time tcis 20 DATA hold time tDIH 20 LRCKI set up time turn 50 LRCKI hold time turn 50 ATT set ...

Page 56: ... 0 5Vdd t tWMSC BCKI DATAI LRCKI p tois yc twai t twSi s X tLRIH X t RIS ATT yf Mode data bit 1 T Mode data bit 16 Mode data bit 16 X MoSe data bit 5 tA S tA h SHIFT L TCH V x t tWLA x tLSn twsF t sz BCKO N DL DH RCKO t3P0 XQ BVD1 Q ZVPO X NVI INVO X tiP3i X X X X X INV02 tipta X X X 52 ...

Page 57: ...FIR2 CTL ATT SHIFT LATCH MODE 7 II R T FIR3 ATT CFST 6 OUT 2 Operating mode setting The operation mode is set between ATT SHIFT or LATCH by transferring mode data Mode data format is in the following format Bit 1 is always set to 0 I att ZH M shift LRjimrniuiiuiiiJirLniirLr atch u When bit 2 is 0 attenuate mode is set when set to 1 system mode is set When LATCH is L data cannot be transferred S3 ...

Page 58: ... MUTE Output zero data ON OFF 5 ATT1 Attenuate data MSB 6 ATT2 Attenuate data 7 ATT3 Attenuate data 8 ATT4 Attenuate data 9 ATT5 Attenuate data 10 ATT6 Attenuate data 11 ATT7 Attenuate data 12 ATT8 Attenuate data 13 ATT9 Attenuate data 14 ATT10 Attenuate data 15 ATT11 Attenuate data 16 ATT12 Attenuate data LSB When the IN IT pin is L the internal resistor MODE1 MODE2 EMP and MUTE are re set to L S...

Page 59: ...TT2 and ATT3 and when their relations are ATT1 ATT3 ATT2 Assume that ATT1 is transferred first followed by ATT2 If ATT2 is transferred before the ATT1 value is reached during state A shown in the figure attenuation directly approaches the value of ATT2 If ATT3 is transferred before the ATT2 value is attained during state B or state C the attenuation proceeds from the value attained at state B or s...

Page 60: ... 3FA H 1018 ATT 20log V 1024 J dB 0 051dB De emphasis De emphasis can be set by two methods which are selected by the CTL pin by a serial transfer of mode data or direct input pin CTL H direct input method L serial transfer Serial transfer of mode data CTL L Emphasis ON OFF is performed by the attenuator mode EMP EMP H ON L OFF Fs Selection System mode Fs 32 and Fs 48 Fs 32k 44 1k 48k Fs32 H L L F...

Page 61: ...IT Output data word length 20 bit 18 bit 7 OFST Append offset ON OFF 8 TEST1 Test mode setting During normal use fixed at L 9 TEST2 Test mode setting During normal use fixed at L 10 NS Noise shaping OFF ON 11 MT1 Zero data detect time Bums 300ms 12 MT2 Zero muting flag polarity Selects de emphasis Fs I O synchronize Stop output clock H sets mute Vsets mute 13 FS32 32K 44 1 K 48K 14 15 16 FS48 SYNC...

Page 62: ...y OBIT OBIT H 20 bit V 18 bit Offset When OFST is raised H output data will have an offset value appended depending on how OBIT is set OBIT H 02AAA H L 02AA8 H Zero data detect time The input data s zero detect time is set by MT1 Refer to the section on 5 zero detect functions for details MT1 H 60ms V 300ms Zero muting flag polarity The zero muting flag FLGL FLGR polarity is set by MT2 Refer to th...

Page 63: ...lock stop When the STAT signal is raised H the internal LRCK 3 cycle output clock LRCKO BCKO and the output data DL DH are pulled L Example with STAT flag raised H LATCH LT STAT J Internal LRC I jT L i n f I h Internal LRCK 3 I cycle section LRCKO BCKO DL and DR are Transferred from uCOM to STAT H nulled L I From here the STAT lag returns to L Mode settings are not limited to SYNC and STAT Whether...

Page 64: ...bit example 1 2 3 4 e 8 10 1 i 3 14 15 16 l7 l8 DC detect Low level delect section section j Zero data detect section structure The low level detect section senses whether the input data s first 14 bit are ALLO or ALL1 The DC detect section senses the input data doesn t change When 16 bit data is input DC detection section consists of bit 15 and bit 16 When 18 bit data is input DC detection sectio...

Page 65: ... When the SYSM signal goes H the zero mute flag is made active When the MUTE ON function in Attenuate mode is used the zero mute flag becomes active LATCH 1 J Max 1 64F t FLGL FLGR X ve I Zero mute flag output timing for the MUTE ON function MUTE OFF operates in the same way INIT re synchronization The zero mute flag is active during INIT re synchronization When INIT is pulled L the zero mute lag ...

Page 66: ...tant to re initialize the system after turning the power on Re synchronization is performed at the time that INtT goes high J initialize synchronization circuit and then positions LRCKI J in the center of the window Operation when I NIT is pulled L Set input data to zero data Set output data to zero data Output clocks LRCKO BCKO 128Fs are continuously output Noise shaper register is cleared IIR re...

Page 67: ...mH C 24nF I Application circuits shown are typical examples illustrating Ihe operation of the devices Sony cannol assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same 63 ...

Page 68: ...SONY GXD2E60M It S J 1 1 rfR E p 64 ...

Page 69: ...ample 0 1990 1 X 0 2000 o o s o o Frequency characteristics 5 0 10 0 Frequency kHz Ripple characteristics 0 0001 0 0000 5 0 io o Frequency kHz 15 0 I 20 0 I o o 50 0 100 0 t o o Attenuation characteristics ire 4 Frequency kHz J li 264 6 552 8 65 ...

Page 70: ...p in SOP Plastic 450m i I 1B 0 3 24 13 ifififlifiUfll r o Cm n o H D H o CM T mumuuuu 0 3 5 M If i ll2 2 ai 1 c 2 Z 0 2 0 jjr x 0 13 I C l 0 3 V ent H c e M 021 rLmmnnnnrtnr SONY NAMEfSDP 24P L101 EIAJ NAMeI SOP024 P 04S0 AU JEDEC 66 ...

Page 71: ...ltage see note Vdd 0 5 to 7 0 V Input voltage Vi 0 5 to Vdd 0 5 V Output voltage Vo 0 5 to Vco 0 5 V Input protection diode current Iik 20 to 20 mA Output protection diode current Iok 20 to 20 mA Output current lo 50 mA Package allowable power dissipation Po 0 8 W Storage temperature Tstg 65 to 150 C Note Unless otherwise specified voltage values are in reference to GND I Recommended Operating Con...

Page 72: ...X and DIF DET Load Window L Active W4 MUT Timing Count Window L Active resTi vJ Yn JBTt 10 TESTS TEST W TjJtsoi LftC y tsos DATA fin HUT L ecK 3 TO MUT R o ur TS hcjTsaa Vr 0 ii i rso Electrical Characteristics Vdd 5 0 10 TA 0to 70t Item Signal Measurement conditions Min Typ Max Unit H output voltage Voh Ioh 4mA 3 7 V L output voltage Vol loL 4mA 0 4 V Schmitt input hysteresis range vt vt 0 85 2 5...

Page 73: ...4 LRCK 1 LR 2ch word clock fs signal 488CK 1 cycle 5 SDATA 1 Serial data signal G BCK 1 Bit clock signal 7 DMUT 1 H forces MUTON t is set during normal operation e Vdd Power supply 5 volts 9 TS04 Test output 10 TS02 Test output 11 MUT R Rch MUT output 12 MUT L o Lch MUT output 13 TS03 o Test output 14 TSOI Test output 15 TESTS 1 Test input Normally set to L 16 GND Ovolt I 69 ...

Page 74: ...it checks whether the upper 12 bits are all O s or all 1 s Direct current detection circuit Detects whether the signal value changes Since all bits up to bit 12 are either all O s or all 1 s this circuit checks only bits 12 through 16 of each word for each channel Also for reading in data both detection circuits use the no change edge of the bit clock data 2 Window generator OX Window The window g...

Page 75: ...l value As a result the MUTE signal is reset on the rising edge on the next LRCK the same occurs with the Rch signal Note The TRST L and R signals are flags showing whether the input data is silence or sound Silence H sound L LRCK _ Silence data Silence data Sound L R L r data Sound dais Sili R nee data S L ence R data Silence data Silence dat L R TRST L v MUT L TRST R r MUT R _ I 4 Forcing a MUTE...

Page 76: ...SONY E a 3 O 3 Sr a 3 Q C P1 72 ...

Page 77: ...age Outline Unit mm 16pin SOP Plastic 30 0roU Z 3MAX l 2 a3 15 9 R B fl B B a II w i lo PS en H u u 1 0 fl MS but B 1 2 7 1 tQh l 2 azMAX 4 04 5 I SONY S AUE SOP ISP L121 EIAJ NAME 30PC16 P D300 AX JEDEC CXE 73 ...

Page 78: ......

Page 79: ...A D D A Converter ...

Page 80: ...D A Converter Type Functions Page CXD2552Q 1 bit D A converter 77 CXD2561BM 1 bit D A converter 3rd order noise shaper 85 CXD25550 1 bit A D D A converter Built in digital filter 2nd order noise shaper 94 76 ...

Page 81: ...0 C 44 pin QFP Plastic 4s Structure Silicon gate CMOS IC Applications Compact disc player digital amplifier BS tuner Recommended Operating Conditions Supply voltage Voo 4 75 to 5 25 V Operating temperature Topr 10 to 60 C OSC frequency fx 32 0 to 49 7 MHz Supply voltage difference Vdo Vdoj Voo DVoo Vdd XVdd 0 1V Vss Vssj Vss DVss Vss XVss 0 1 V I Block Diagram and Pin Configuration ill s s 3i iHtH...

Page 82: ... DR Rch data input 16 DLI Lch data Input 17 BCKI BCK input 18 TEST1 Test pin Fixed at L level in normal operation mode 19 TEST2 Test pin Fixed at L level in normal operation mode 20 SYNC Sync control pin 21 INIT Resynchronized by rising edge of this signal 22 128Fs 128Fs output 23 Vsub Sub straight Connect to GND 24 512Fs 51 2Fs output 25 DINIT Delay INIT signal output 26 INAF When I O sync is mis...

Page 83: ...e DINTT INAF Vol lo 1 mA 0 4 V H output voltage 512Fs LRCKO VOM lo 0 4mA Vdd 0 5 V L output voltage 512Fs LRCKO Voi lo 0 4mA 0 4 V H output voltage 128Fs VOH lo 0 3mA Vdd O 5 V L output voltage 128Fs Vol to 0 3mA 0 4 V H output voltage R R U L Voh lo 1 5mA Vdd 0 5 V L output voltage R R L L Vol lo 15mA 0 5 V H output voltage XOUT Voh I o 2 0mA Vdd 0 5 V L output voltage XOUT Vol I o 2 0mA 0 4 V Cu...

Page 84: ...SONY CXD25523 Input BCKi DATA L fl LRDC1 Output PLM OUTPUT I I troJm PLf ss 90 Vdd 10 Voo tfplm 80 ...

Page 85: ...N ratio S N 1kHz OdB dB data Fs 44 1kHz A fitte used 96 dB Electrical Characteristics Testing Method The testing of total harmonic distortion and S N ratio is shown in Fig 1 and 2 100P SHIBAS0KU flD725C Fig 1 384 Fj 3 multiplier BFs CIRCUIT DIGITAL SIGNAL GENERATER 158 T D F CCXD1244 OLI osc SHIBAS0KUIAD725C DAC 1CXD2552 l m ANALOG CIRCUIT ANALOG ANALOG SWITCH BOX DISTORTION ANALYZER Fig 2 81 ...

Page 86: ... 2 Resynchronization by means of INIT Even when LRCK X is inside the window but located close to one of the two edges of the window synchronization may be upset by the mingling of external noise To this effect it is necessary to apply resync without fail after power supply is turned on Resync operation is executed from the rising edge of INIT and timed after 4 periods of Fs rate LRCK The sync circ...

Page 87: ...SONY I 41 Si s_ A 41 3 i o A j3 _A i 6 i 6 4 6 1 11 if s B i c e S 1 U Id Is I 9 2 C A a d 3 a s 2 IE i A3 I 83 ...

Page 88: ...SONY CXG2552Q Package Outline Unit mm a f i n C r P L a S t i c 1 1 g Q17 S SONY NAME QFP 44P L12 EIAJ SAME QFP044 P l i4 AX JEDEC CODE 1 84 ...

Page 89: ...acteristics Distortion 0 0035 and below S N ratio At least 95dB Features 2 channel D A converter on a single chip Srd order noise shaper PLM method pulse conversion output Master clock ot 512fs Structure Silicon gate CMOS Applications Compact disc players digital amplifiers satellite broadcast tuners etc Pin Configuration Top View I DVoollJ TEST 2 initQ lrckM DATAR T DATAL J DVss 512FS 9 XVss 10 X...

Page 90: ...e Vdc 0 5 6 5 V Input voltage Vi 0 3 Vdd 0 3 V Allowable power dissipation Pd Ta 60 C 500 mW Storage temperature Tstg 55 150 V Recommended Operatir g Conditions Item Symbol Conditions Min Typ Max Unit Supply voltage Vdo 4 75 5 00 5 25 V Operating temperature Ta 10 60 C OSC frequency Fx 512fs 16 0 25 0 MHz 86 ...

Page 91: ...T Crystal oscillator output 512fs 13 XVdd Clock power supply 14 Vsub Connected to substrate GND 15 AVddR Analog power supply for right channel 16 R1 o Right channel PLM output in phase 17 AVssR Analog GND for right channel 18 R1 Right channel PLM output opposite phase 19 R2 Right channel PLM output in phase 20 R2 Right channel PLM output opposite phase 21 AVdd Analog power supply 22 AVss Analog GN...

Page 92: ... 4mA Vdc 0 5 V L W VoH lo 15mA Vdd 0 5 V XOUT VOH lo 2 0mA Vdd 0 5 V Low level input voltage 512FS Vol lo 0 4mA 0 4 V Vol lo l5mA 0 5 V XOUT Vol lo 2 0mA 0 4 V Current consumption Idd 40 60 mA AC Characteristics DVpp XVoDaAVDD AVDoR AVopL 5 0V 5 DVss XVss AVss AVssl AVssR 0V Ta 1 to 60 1 Item Symbol Conditions Min Typ Max Unit BCK pulse width tw 38 40 nsec DATAL DATAR setup time tsu 18 20 nsec DAT...

Page 93: ...S lft 0 PLM OUTPUT 10 Vdd tr CPLM r tr cplm r I Analog Characteristics DVdd XVdd AVddR AVddL 5 0V 5 DVss XVss AVss AVssUAVbsR OV Ta 25 V Item Symbol j Conditions Min Typ Max Unit Total harmonic distortion factor THn 1kHz OdB data mu Fs 44 1kHz 0 0035 S N ratio S N 1kHz O 00 OdB data Fs 44 1kHz 95 dB 89 ...

Page 94: ...s shown in Figures A and B Figure A 220p 1O0P 4700P w r j r t 6k v k 5k 1 mwh AD7ZSO SHIBtSOKU L R c fi Select er DISTORTION ANALYZER Figure B K UJTIPLIER 128Fs 3841 DIGITAL SIGNAL GENERATOR C16BIT s WTA 512Fs D F CXD2560 8Fs _ w DAC CXD256I OOP PLM L PLM ANALOG CIRCUIT a 1 SHIBASQKU CAD725C ANALOG SWITCH BOX DISTORTION ANALYZER 90 ...

Page 95: ...is LSI to external systems Resynchronization by INfT If the LRCK J is within the window but is too close to either sides of the window synchronization may be affected by factors such as external noise Thus it is always necessary to resynchronize after power is switched on Resynchronization is done at a timing of approximately four cycles of LRCK at the Fs rate from the rising edge of INIT and it i...

Page 96: ...SONY CXD256 BM o c o Q Q i it 5 8 I n it ZJ C l si St Is Is II o e S O I is 8 ii if 92 ...

Page 97: ...SONY Package Outline Unit mm 28p i n SO Plastic 375mi L 17 75 SI S3 NY IWfcl S OF 28P L121 E1AJ UAW i S3 3 CtB P S3tlO AX JEBEC CODE I 93 ...

Page 98: ... within 0 01 both AD and DA S N ratio DA converter At least 90d8 AD converter At least 80dB Structure Silicon gate CMOS Functions On chip digital filter enables data input output at rate of IXFs Simple connection of multiple CXD2555QS enable multi channel system The 32 slot serial data interface enables in dependent selection of data forward packing rearward packing and MSB first LSB first Applica...

Page 99: ...lock 7 XTLI Crystal oscillator circuit input Connect the crystal oscillator selected by the 1 crystal oscillator selection pins XSLO to XS12 Pins 34 35 and 36 Input for external master clock 3 XTLO Crystal oscillator circuit output Connect the crystal oscillator selected by the crystal oscillator selection pins XSLO to XSL2 Pins 34 35 and 36 9 Vss GND for master clock 10 vS Analog GND for Channel ...

Page 100: ...per 1 sample serial data input Data format is based on the complement of 2 32 bit slot 30 SOUT 2 channel per 1 sample serial data output Data format is based on the complement of 2 32 bit slot 31 v5i GND for digital circuits 32 MASL For serial I O with 16 bit serial data selects either the first 16 bit slot or the last 16 bit slot of the 32 bit siot High means forward packing low means rearward pa...

Page 101: ... Min Typ Max Unit Supply voltage v 4 5 5 0 5 5 V Operating temperature Ta 20 75 c Sampling frequency Fs kHz Note The analog power supply Pins 17 and 44 must be turned on at either the same time or before the power sources Turning this power on after the other power sources may cause latch up There are no specific limitations on the order in which power supplies are turned off Input Output Capacita...

Page 102: ...t 1 lui 10 10 pA 7 Input leakage current 2 lis 40 40 aA 8 Output leakage current Iss 40 40 A 9 Feedback resistance Rf Z Vin Vss or Vnr 250k 2 5M Q 10 1 During input to all input pins except AIN1 and AIN2 and bi directional pins BCK and LRCK 2 AIN1 and AIN2 3 XCLK XMCK2 and SOUT 4 AOUT1 AOUT1 AOUT2 AOUT2 and UCLK 5 XTLO 6 During output from bi directional pins BCK and LRCK 7 All input pins except A...

Page 103: ...n also be selected independently by MLSL to be either MSB first or LSB first MASL High forward packing Low Rearward packing MLSL High MSB first Low LSB first Master mode slave mode Related pins MS LRCK BCK When either connecting several CXD2555Qs together or pairing one CXD2555Q with a CXD2558M put one of the CXD2555QS in use to master mode to act as the supply source to LRCK and BCK The other CXD...

Page 104: ...LK xsu CXD2555Q XSLO XCLK XTLI XTLO Jr m To external C e g DSP To CXD2555Q in s ve mode etc 1024Fs Crystal oscillator frequency selection Fs 8 to 24kHz Related pins XTLI XTLO XSLO XSL1 XSL2 UCLK XCLK WhenXSL2 is fixed at High the CXD2555Q can be set to operate at 1 2 or 1 4 of the usual Fs frequency in this case also the frequency of the crystal oscillator can be selected by a combination of XSLO ...

Page 105: ...SONY CX02555Q s rt f I 1 s I en 03 I II rih n 5 op X to m I C M W I I 101 ...

Page 106: ...SONY CX 25f5Q t i I _ te i fa SsQQ 9 s 1 S S Zl2SS2St gEEEEc c 5 Q Q S ra ra ra m li c H Q issaslIIIIH jHrirHMinnuimm Oil 2 I l 5 C A3 S 5 2 li 102 ...

Page 107: ...SONY CXD2S55Q Package Outline Unit mm 48pin QFP Plastic 0 7g D15 3 w KM _ 0 1 5 0J5 I01 0 15 I E S 02 M S EIAu NAME QFP 48P 104 QFP04B P 1212 B uEDEC DODE 103 ...

Page 108: ......

Page 109: ...ADSP Audio Digital Signal Processor ...

Page 110: ...arious digital audio data Double accuracy arithmetic possible 107 CXD1355AQ Programmable DSP and 8fs over sampling digital filter for surround 159 Programmable DSP Equalizer for surround CXD2701Q Characteristics realized by fixing algorithm at equalizer 179 and giving coefficient from exterior I Of ...

Page 111: ... instruction RAM 24bitx64w coefficient RAM 16bitx64w data RAM 16bitx64w 16bitx16bit built in multiplier data coefficient 1 16x16 1 cycle 2 16x32 2 cycle 3 32x1 6 2 cycle 4 32x32 3 cycle 34bit 34bit Ace 34bit with 2bit shifter For adder subtracter R H L Serial I O 1 1 H L I 2 H L O 1 H L 2 H L Delay I O D1 H L D H L Every register 32bit H L can be used independently CXD1160AP 2Spin DIP Plastic CXD ...

Page 112: ...in Max Supply voltage Voo Note 1 Vss 0 5 7 0 V Input voltage Vi Note 1 Vss 0 5 Vdd 0 5 V Output voltage Vo Note 1 Vss 0 5 Vdd 0 5 V Operational temperature Topr 20 75 c Storage temperature Tstg 55 150 c Note 1 Vss 0V Block Diagram XOVF Note Pin numbers are those of CXD1160AP 108 ...

Page 113: ...ses a delay line for 2 channels 6 TST I Test pin Normally fixied to GND 7 Vss GND pin 8 MCK1 i Master clock input 1 Master clock ACK inside the IC is half this frequency To input the master clock through MCK1 fix MCK 2 to 5V 9 MCK2 I Master clock input 2 Master clock ACK inside the IC has the same frequency To input the master clock through MCK2 fix MCK1 to 5V or to GND 10 SI I Input pin for 1 sam...

Page 114: ... DRAM 27 DIO I O Turns to serial data input pin when DYSL is at L and takes in according to the various serial I O modes Turns into external DRAM data I O pin when DYSL is at H to assume a common bus with DRAM data input Din and data output Dout 28 XCAS External DRAM column address strobe output pin Pin Configuration and Pin Description CXD116QAQ Pin Configuration HHHHHHHHHHHHHHHHHHHHHHH 65 80 c T...

Page 115: ...tion output Outputs V during overflow detection 32 33 N C 34 A6 O External DRAM address output A6 35 A3 o External DRAM address output A3 36 A4 External DRAM address output A4 37 AS External DRAM address output A5 38 A7 o External DRAM address output A7 39 43 N C 44 XCLR II Test pin Normally fixed to 5V 45 48 N C 49 Vcc 5V supply pin 50 55 i N C 56 A1 Extern af DRAM address output A1 57 60 N C 61 ...

Page 116: ... I O Fixed at 5V it turns to delay mode Connected to an external DRAM 64kbit composes a delay line for 2 channels Recommended Operating Conditions Item Symbol Min i yp Max Uf it Supply voltage Vdd 4 5 5 0 5 5 V Operating temperature Topr 20 75 c Electrical Characteristics DC Characteristics Vod 5V 10 Vss 0V Topr 20 to 75 C Item Symbol Conditions Min Max Unit Output voltage 1 I 1 luvel 1 Von 1 loH ...

Page 117: ...he actual physical address and can be handled as a delay tap fixed address 4 Data Register all in complement on two format 511 Register This register 32b stores CH1 data input from serial I O used for read only Upper 16bit 11 H and lower 16bit ML can be handled independently 512 Register This register 32b stores CH2 data input from serial I O used for read only Upper 16bit I2H and lower I6bit I2L ...

Page 118: ...g K D K X X D and X X Also 4 multiplying modes 16b 16b 16b 32b 32b i6b and 32b 32b Selects either ACC or O by means of AU command Selects either P 33b or H 32b to convert into 34 bit length Data selected by means of the above 2 selectors is either added subtracted turned into absolute value or compared together When ACC data is transferred or multiplied or sent to the below mentioned barrel shifte...

Page 119: ...en according to MPY mode in 1 2 3 cycle time The number of cycles that can be executed within 1 sampling section depends on the sampling frequency fs and the cycle clock fKCK fiCK Let s assume that at sampling section 1 we have L cycle cycle to cycle L 1 Here the last cycle L 1 called KSH cycle cannot be executed because of the command or coefficient transfer section of the microcomputer interface...

Page 120: ...ddress n9 address 1 can be used Here low word Ki_ is stored in n address and high word Kh is stored in n 1 address 16 b m Ks 64 n n 1 kd W K RAM address specify can be mentioned in the command that actually handles K RAM There are 2 types of K RAM address specify absolute address specify and relative address specify Absolute adderss specify Absolute address addr Relative address specify addr relat...

Page 121: ... DAC because the physical address Physical address DAC addr Example Logical address is assigned to the respective data in the formula at right If y n is entered in addr 3 and X n in addr 1 then y n 1 is constantly in addr 2 and X n 1 in addr Q formula y n k y n kiX n ks X ii n t t 1 addr 3 2 10 hysical address 4 3 2 1 DAC 0 n vCn yCn 1 KiO Kn 1 DAM r l n yCr y n I Ke X n l X n 2 I D RAM address sp...

Page 122: ... pin MCK1 Fix input pin MCK2 to 5V fwc 2f ACK 2 When the input is from input pin MCK2 Fix input pin MCK1 to SV or to GND In any case the maximum frequency of master clock ACK is f S15 36MKz 18Kx32M Moreover as this IC makes use of a dynamic F F internally it is not possible to stop the the master clock and keep the internal condition as it is Cycle clock ICK or KCK inside the IC is twice ACK maste...

Page 123: ...sted When this IC is used as a multi processor all SDT pins or SCK pins on the respective IC s may be linked The transfer format shown later on timing system features serial data from SO top bit to S39 as shown in the big below SDT SCK XSLD j r td l W n L_rL_n_ ltlj LTV L_r tLwH Ids 0 Urn MACK 1cl 0 U l 2ACK tdtl MACK ton MACK L 3ACK U h 2 n DACK Oi DKCK for n DKCK LRCKSnKCK I By applying the belo...

Page 124: ...S13 S14 K12 KI3 K14 112 1 13 1 14 S15 K15 115 S16 K16 116 S 1 00 S17 KIT 117 S 1 01 S18 K1S 118 S19 K19 119 D 1 S20 K20 120 S21 K21 121 S22 K22 22 ST K23 123 MUTE S 24 S23 K24 K25 526 K26 S27 S28 K2T K28 S29 K29 S30 K30 S31 K31 MSB L H S32 KAO CLSB 1 AO LSB S33 KA1 1 Al S34 KA2 1 A2 S35 KA3 1 A3 S36 KA4 1 Al S3T KA5 CMSB I A5 MS11 S 38 S 39 L H H In brackets respective modes proper value Between d...

Page 125: ...nds to K RAM in the instructions too 2 I mode This mode transfers instructions to l RAM 24 bit x 64W S39 is at H and S 31 at IA5 MSB to IA0 LSB 6 bit specify l RAM address IA address to 63 To this A address 123 to 10 24 bit are Input 3 R mode This mode transfers information relative to the setting of serial I O and Oelay I O S39 is at H and S31 at H too Beside this setting is executed at pins DYSL...

Page 126: ... GND X X 32 clock 32 bit 32 bit 5V L L 24 clOCk 16 bit 24 bit L H 24 bit 24 bit ii H L 24 bit 16 bit H H 16 bit 16 bit 3 R9 to RO Sets the delay sample quantity common to Delay I O delay mode 2ch number of delay samples R9 SH 87 B6 R5 U u RO Number of delay samples L L L L L L L L L L l H fl H H H H H H H H 2 H H H H H H II II II H 3 H H H H H H H H H H 4 L L I I L L L L H H 10 2 2 L I L L L L L L...

Page 127: ... bit units Reg 11 11 I2H I2L 01 01 02H 02L Contents Channel 1 input high word register Channel 1 input tow word register Channel 2 input high word register Channel 2 input low word register Channel 1 output high word register Channel 1 output low word register bit length 16 16 16 16 16 16 Channel 2 output high word register 16 Channel 2 output low word register j 16 R W R W RAW R W R W Bit express...

Page 128: ...h2 input registers T ch1 ch2 output registers value latched at shift register Serial I O and I O register are dependent on the timing with LRCK and BCK from the exterior Also the only interrupt is executed between this LRCK and BCK on the Instructions The IC operates on the master clock Now should the operation be going on in 1LRCK period at cycle to cycle L L 1 cycle the following restrictions wo...

Page 129: ...H B 3 1 B 3 Bit B i a 2L Bl j Bm Bl Ba MSB LSB MSB LSB 01H d C s C 7 Ci j OIL Cii C C C 02H D D30 Bit D j 02 L Di On D Do If all data is handled as 32 bit data then we have 2ch IN 2ch OUT If all data is handled as 16 bit data then we have 4ch IN 4ch OUT Mixed handling in single precision 16 bit and double precision is possible Example of Single precision numerical expression I 1 I H A X J JUi I 1 ...

Page 130: ...sb I IH I 1 L Ai s Am Ai Ao 2H x x I 2 L B L A B L 1 B Dm MSB LSB 8LSB 01H Cj Lao C i t C i a 01 L Cis Cii Cs 02 H D 3 Ds Di D s 021 D s D M B x X Input register enters on low word register side Output register is at lower 8 bit don t care Example of single precision numerical expression 1 1 L Ai S 2 Kit Example of double precis or numerical ex pression 1 H C t 2 As C I 2 C 1 26 ...

Page 131: ...m Ah I 2H Bi i H a B B I 2L Bi j Bi 4 MSB LSB 1H C3 1 Cj d Ci 01 L C I I 02H Dii Dt 0 Dn 02L 0 Dm D X X is input in the lower 8 bit of the input register while the output register lower 8 bit are at don t care 24 bit 2ch IN 24 bit 2ch OUT Can be handled as the data between 16 bit and 8 bit Example of single precision numerical expression 1 1 H A I 2 A I iL 4ii I S At Ai 2 A Example ot double preci...

Page 132: ...ll Aso Ai T Aii I 1 L Am An A 1 2H B31 B3U PI T Bt fl I 2 L B 1 B B s Mib 01H Cii Cao C 7 C 6 01 L x X 02H D11 Dm D T D OZL x X In the input register lower 8 bit there are eight O s The output register uses the high word side Accordingly 01 L and 02L are used as temporary registers Example of single precision numerical expression 1 h cs i r Cu Example ot double preci sion numerical expression 1 1 ...

Page 133: ...ssml xes Register MS3 LSB 1 1 H Aai Ajo Ait An 1 1 L x x I 2H Ba i Bi g Bit Bi I 2L X X MSB LSB 1 H Cii Cf a Ci t Ci OIL X x 02H 1 D S Dig Bit Dm U L As the input register uses high word register only Accordingly ML and I2L are not use 01 L and 02L are used as temporary registers Example of single precision numerical expression 1 1 H A 2 A 129 ...

Page 134: ... Eie for E 5 E 2 When used as double precision register 32 bit DIH L and DOHA come in pairs That is when DIH is specified numerical expression turns out as MSB at E31 and LSB at EO for L E Z r B as much as similarity with serial I O register is concerned However there is a decisive difference where the following points are concerned In serial I O register two 32 bit stereo for ich each are availab...

Page 135: ...ll ISO Section where gate latch is 1 applied to Dl register DO register value is latched to shift register Dl register value contained in the first half of 1LRCK calculating operations is the serial input data of the second half of the preceding LRCK Dl register value is similarly the serial input data of LRCK first half Also the value entered to DO register in the first half becomes the serial ou...

Page 136: ...lows LRCK XWSO WE DO register Dl register J u 1 u CH2 n 1 X CHIInl X CH2 nl X CHUn il X CH2 n 1 r J CH1ln r X CH2ln r X CH1 rv 1 r X Calculating operations DO register indicates data entered in the last part of that space That is if data CH1 n is written in DO register of 1 LRCK calculating operations first half then data CHI n r can be read from Dl register If data CH2 n is written in DO register...

Page 137: ...67 6S 93 100 101 102 133134135 kck ruw nnnsu rmjuu juuuu njuiRr ksl n n xras J _ _TT XCAS XWSO WE U JOT S u xu u ru u nr v i i A7 A5 EOC 3XDC DEDC ZKZEDC DEDC A4 ao WOIB IGDKOIK XHKOB XEKJOSt JdUKOE do o a n a a di oo oo i t Calculating operations I Should the data written last between cycle to 66 in DO register be at CHl n data CHl n r from the previous cycie 134 up to the present cycle 65 in Ol ...

Page 138: ...bit contain 0 Timing LRCK 128KCK Example 126127 29 30 31 32 61 62 63 64 93 94 95 96 125126127 kck nruTJ rLnrLru nnjuu jump jltloju KSL PI PI _PL _pl PL XRAS _PL_ xcas i u sir u ru u nr XWSCXWE1 i A7 A5 ECX JZOC L_ 3XO A4 60 xzran xuxxod hieds m do a a u n Dl oo PJECX i 29K n oi a Calculating operations Should the data written iast between cycle to 62 in DO register be at CHl n data CH1 n r from th...

Page 139: ...ess set by the user becomes the actual value Single precision data and double precision data 2W mutually separated by 32 addresses can be used in this order or otherwise MPY Command 4 Types K D K X X D X X and 4 kinds of modes 16b 16b 16b 32b 32b 16b 32b 32b can be handled Through the respective modes the execution cycle of the command is determined K K RAM value D D RAM value X From the register ...

Page 140: ...channel 2 output high word register and low word register 02L 16 aw D1H 16 R Delay I O input high word register and low word register D1L 16 R DOH 16 W Delay I O output high word register and low word register DOL 16 W RH 16 W High word register and low word register for AU operations RL 16 W P 33 Register where multiplication results are entered Ace 34 Register where AU operation results are ente...

Page 141: ...r K 1 During single precision command word of K addrj is handled During double precision command 2 word 32b of K addr and K addr 1 are handled Here IU d Tl 2 dn jdr Kj addr 9 IS IT 16 a 3 a2 al aO 7 16 al aO I With K addr at low word K addr 1 at high word 1 increment from the addr specified by the user addr 1 addr execution is completed For commands where K RAM is not handled the present address r...

Page 142: ...0 H a5 s4 a i i2 al aO 12 15 14 13 12 11 10 L a5 a4 a3 a2 al aO 13 12 ii io At absolute expression 0to63 At complement on 2 expression 32 to 31 At complement on 2 expression a3 a2 al aO 8 to 7 II 10 At complement on 2 expression al aO 2 to 1 addr D addr D l During single precision command 1 word of D addr is handled D s di I r d n During double precision command 2 word 32b of D addr and D addr 1 a...

Page 143: ... out as follows It I21 I20 L L L H H 1 H K 123 122 K D K X X D X X L L L H H L H H K16 D16 K16 D32 K32 D16 K32 D32 Si 6 X16 K16 X32 K32 X16 KS2 X32 X16 D16 X16 M2 X32 D16 X32 D32 X16 X16 X32 X32 For X X with MPY command either 16b 16b or 32b 32b is used However for transfers where double precision X is at the source X16 X32 type can be used Multiplication results enter register P and can be used w...

Page 144: ...lts from the previous command It is code expanded to 34bii for use R stands at a 32bit value as entered in R register by transfer commands from the commands received up to that it is similarly code expanded to 34bit for use There are 5 Flags for the multiplication results of AU commands to be used when the following command is a conditional jump command However where X mark is shown on the above c...

Page 145: ...gh word register Whether the transfer command is of single precision or double precision depends on the transfer origin source That is determined through I23 and I22bit of MPY command MPY command uses for X X 16b 16b I23 I22 LL 1 cycle or 32b 32b 123 I22 HH 3 cycle Should the multiplication be ignored can be executed at 16b 32b I23 I22 LH 2 cycle IS IS 17 16 X 19 IS 17 16 Y 13 12 11 10 13 12 11 10...

Page 146: ...specified in the 4 bit to dn Conversion scale is for also included to 15 bit S 2 2 S 1525 HO Input data to be converted is 31 bit data A excluding LSB taken from value A 32b or the result value Ace from the previous command passed through a clipper A tj a I 2 ajl 1 2T SA S 1 The converted results can be observed from the following 4 registers The value is kept until the following barrel shifter op...

Page 147: ... into the regular form BOiHs bt l Case 11 2 AT o 2r a i sr ui i o zr s i 2 5 boih 2 This becomes r BO 1 HCd 0 Q 15 Arithmetic lett shift With sign bit fixed S bit of Av is shifted left 0 1 R 8 X2 a vi Case I 2 A S A s I 0 Z2 a l 2 5 S2 tn il 2 Z2 a 0 12 aji i BOl H Case I A S 2 5 A 2 i 1 lY a s i 2 r2 a7r 2 J 2 I 2T i 2 in T 2 a i 2 _ 1 2 aii as l 12 1 BO I H CaseUI A r 2 or 2 AC in this case conv...

Page 148: ...sitive value floating point conversion is executed from that bit Shift Q Q 2 Hi q becomes the Flag BSQ That flag value is kept until the following barrel shifter operation command comes When condition jump command and barrel shifter operation command are on the same command Flag BSQ that is utilized for condition jump is the flag value of the previous barrel shifter operation command BSQ ON The bi...

Page 149: ... previous commands Acc 0 L L H Non zero Results of previous commands Acc 0 L H L Plus Results of previous commands AccSO L H H Minus Results of previous commands Aco 0 H L L Over flow Results of previous commands Acc 1 or Acc 1 H L H BSQ Barrel shifter operation command positive value floating point type conversion up to the previous command is odd numbered shift bit H H L keep 1 Actually same val...

Page 150: ...ead address Loop address set LPS Loop jump LPJ 115 111 110 15 14 L H H 115 111 10 15 14 L L H Pushes the next instruction address loop head address into the next instruction address Decrements the loop counter value T C 0 jumps to the address in the stack C 0 Pops out the stack and proceeds in order to the command of the following address Example Program LTS 1 Command group A LPJ Command group B E...

Page 151: ... K LPJ RTN LPS Acc Acc Ace Y D 3 id i setting LPJ RTN LPS K i K6 J Y A I LPJ RTS LPS w l VI W j M j I x rx y 1 Ki i r Acc Ace Y LPJ RTIUPS X D Ht d r CLPJ RTN LPS E K Bi id rl D Y CLPJ RTX LPS s c K 1 c o4 I iLCS CC LTS CO I Rfi a k2 a 5T JMP W CAL A I JMP fJU CAL A I Dt X X D id rl LPJ RTX LPS I I 1 1 1 I 5 C K4 C X K X LCS CC LTS CC I I i De Acc I d rl Acc Y LPJ RTK LPS E X X X Y LPJ RTN LPS I 0...

Page 152: ...lus Minus Over flow BSG keep keep iii no J none 1 LPJ 1 RTN l i LPS 19 18 17 16 Y 3 12 11 10 1 Assignment when transfer command is not to be given 10 11 RR RL R register 10 10 1 110 111 01H O 1 L 02 H 2 L Serial I O CHI Output register Serial I O CH2 Output register 10 10 1 DOH DOL Delay I O Output register 10 10 10 11 110 B 1 1 H B I 1 L B I 2H Positive value floating point type Arithmetic left s...

Page 153: ...on possible Cycle N 2 KSL cycle with the exception of K RAM access execution possible Cycle N 1 KSH cycle Execution impossible Any command will do To provide time for K RAM I RAM and the micro computer to interface and are available The number of cycles N is given through the following formula with fs for sampling frequency and fkck as cycle clock frequency fs fs for fkck HAex 1 fv if If fkck is a...

Page 154: ...to normal cycle or KSL cycle Execution possible with the exception of K RAM C cycle Ni 1 Turns into KSL cycle or KSH cycle A command that does not use transfer command In fact execution impossible D cycle N1 Turns into KSH cycle or does not exist Execution impossible Any command will do Example 1 When fkck 6 144 MHz fs 48 KHz fkck fs 128 N Ni 128 Cycle to cycle 127 Cycle to 125 Cycle 1 26 Cycle 12...

Page 155: ...necessary fKCK fS for whole number n iN 4 Srt SN 1 I Ni 4Sn 5N I Cycle to cycle Ni 5 Serial input data transferred to the previous sampling space is in this space register and can be handled freely Cycle Ni 4 to cycle Ni In this space usage of serial I O input register is prohibited 2 Serial I O output register Cycle n conditions for transfers that can not be executed with serial I O output regist...

Page 156: ...ble Cycle 124 to cycle 127 unusable 1 3 I Serial I O output register 24 clock system i 4 128 n B Z 128 4 48 4 48 B lSn 1 1 n K l K 1 127 Cycle 127 unusable 11 3 1 Serial I O output register 32 clock system N 4 128 n N 2 128 N 2 J n K 4 4 H 2 n fiH 1 n 1 B ZSn SN 1 I N 2 sn 1 11 1126 Sn S1Z7 f Cycle to cycle 125 usable 1 Cycle 126 to cycle 127 unusable 152 ...

Page 157: ... input register Delay I O input register is input twice during 1 sampling period For one of those 2 instances the timing is the same as for serial I O For the other instance the conditions for the transfer with this register as source or the cycle n when MPY cannot be executed are 1 fKCK 1 I fKCK 3 4 n 2 M 2 fS 4 2 fS 4 as n ckck 2 1 H 1 fKCK 1 2 fS 4 2 fS 4 1 fKCK 1 accordingly n a i iaxn n 4 I I...

Page 158: ...tem 25 fKCK 1 25 48 fS 4 48 IRQ fS 4 32 bit clock system 33 fKCK 1 33 84 fS 4 n 64 fKCK fS 4 ln certain cases as the left side margin is not included cycles that become prohibited are not included Please check when necessary Example 1 tkck 6 144 MHz fs 48 kHz N Ni 128 Cycle to cycle 127 1 1 1 Delay I O input register i 128 4 60 n 6 Cycle to cycle 59 usable Cycle 60 to cycle 61 unusable Cycle 62 to...

Page 159: ...register n _ 139 3 4 65 4 n 65 Cycle to cycle 65 usable Cycle 66 to cycle 67 unusable Cycle 68 to cycle 134 usable Cycle 135 to cycle 139 usable 25 I 25 3 Delay I O output register 24 clock system 139 3 4 n 139 3 a 68 3 n 69 8 n 69 Cycle 1 to cycle 68 usable Cycle 69 unusable Cycle 70 to cycle 137 usable Cycle 138 to cycle unusable 33 33 3 Delay I O output register 32 clock system 139 3 4 n 139 3 ...

Page 160: ...n this period CH1 data n r can read 1 Cycle 62 to cycle 125 In this period CH2 data n r can read I Cycle Ni 1 Ni read prohibit 2 30 bit delay mode 30 bit Conditions where delay mode can be realized fS fKCK that is 123 N il28 The relation between data to write in DO register and data to read from Dl register is DO register Cycle to cycle 62 Cycle 63 Cycle 64 to cycle Ni 2 Cycle Ni 1 Ni data written...

Page 161: ...SONY CXD1160AP AQ Application example 1 Microcomputer CAS DO DRAM for WE DelaV CD CXD1125Q Application example 2 I 157 ...

Page 162: ...P AQ Package Outline Unit mm CXD1160AP28pin DIP Plastic 600 mil 4 2g 36 m 25 is o U U U U U U u UUUUU jl 1 2 54 a 3ST i s rr 0 tO15 a wmwmftt 0 5 3 12 U OIP 2SP 04 CXD 1 1 60AQ 80pin QFP Plastic 1 6 g 2 3 9 0 1 158 ...

Page 163: ...field processing pre processing down sampling fs fs 2 and post processing up sampling fs 2 1s External delay RAM 64kx4bit or 256kx4bit Internal coefficient RAM or DSP functions and command RAM Delays up to a maximum of 64k samples tor both L and R channels Built in 2 channel oversarnpling digital filters for handling 8 times 4 times oversarnpling Filter characteristics Ripple 0 001 dB or less 0 to...

Page 164: ...e H Channel 1 data transfer active 5 BCK02 Bit clock output with weak output signal of 192fs frequency 6 VSS1 GND 7 BCKOI Bit clock output 192fs frequency 3 DATAL Serial data output Data format is 2 s complement MSB first 81s mode L channel output 4fs mode L channel R channel output 9 DATAR Serial data output Data format is 2 s complement MSB first 8fs mode R channel output 4fs mode made active by...

Page 165: ...ternal DRAM address output A5 33 A6 Externa DRAM address output A6 34 A7 External DRAM address output A7 35 A8 External DRAM address output AS 36 TEST I Test pin Fixed at GND in normal operation mode 37 OFST I Offset select input H offset L non offset 38 DPOL I Input data for inverted non inverted select H inverted L non inverted 39 Vdd2 Power supply 5V 40 PRGD I Serial data input for receiving in...

Page 166: ...voltage 3 HM level Voh Output mode I oh 2mA 2 4 V 7 L level Vol Output mode loL 1mA 0 4 Output voltage 4 H level Voh loH 2mA 2 4 V 8 L level Vol loi 1 mA 0 4 Output voltage 5 H level Voh loH 4mA 2 4 V 9 L level Vol loi 2mA 0 4 Input leak current 1 Ili Vi Vdd 0V 5 uA 1 3 Input leak current 2 Ili Vi Vdd 0V 10 nA 2 Input leak current 3 lu Vi VodJW 20 pA M Input leak current 4 Ili Input mode Vi Vdo 0V...

Page 167: ...ut acK t wis twia tins tlDH DATA V M C J7 tlLRH tlLRS LRCK X don I care Output BCKO DATAL DATAR WCKO LRCKO APT twOB twOB V tOH 3 tov f V Undefined PRG input PR6D XI Ipos tpDH RGCK f f M t PR 1 PR tPR _ PRGL tWLT i TPR lfcr Ctn PRGL V t LI V J 163 ...

Page 168: ... Input data hold time Iidh 20 ns Input LRCK set up time tiLRs SO input LRCK hold time tlLHH 50 Output BCKOI pulse width tWOB T 1 fXT CL 50pF T 15 T T 15 ns Output signal hold time tOH Output signal define time tov 15 PRG input base timing tPR 100 ns PRGD set up time PCS 100 PRGD hold time tPDH 100 PRGL rise time tTL 200 PRGL fall time tfL 200 PRGL pulse width tWLT T 1 fXT 4 T ns PRGL pulse interva...

Page 169: ...RR 2fs 4fs 3rd FIR C4f5 8fs ATT DOFF I LIMITTER D RAM Items marked with asterisk are data transferred trom the microprocessor DPS PRG DPS program LPF 1 ao ai 32 as a4 LPF 2 bo bi bs ba b4 IIR filter coefficients mo rrn Mixing coefficients ATT Attenuator value Mo Mi M2 MODE de emphasis noise shaping DRAM select At power on all values are undefined Z V 1 sampling cycle delay PI SO Output 165 ...

Page 170: ...et settings OFST 18 16 Offset value Output DATA bits Offset amount H H 02AAh00b 18 1 L 02AAh 16 L H OOOOhOOb 18 0 L OOOOh 16 Note that the upper 16bits of the 18 bit DATA word represent 4 digit hexadecimal numbers whereas the lower 2bits represent 2 digit binary numbers iii Output mode settings 8 4 18 16 Output DATA Output pin contents DATAL DATAR H H 8fs 18 bit LCH RCH L 8fs 16 bit LCH RCH L H 4f...

Page 171: ...of this signal initiates an interna request for processing DSP When set V the DSP program and K RAM data transfer unction is disabled MIX coefficient is fixed at m0 1 m1 0 This transfer format next item timing are shown in the figure below PRGCK z j 5 s J t 9 10 i ID l a l IT l ZO 1 2 M S 1 bit When set L transfers DSP information when H transfers non DSP information L 7 bit Identification label f...

Page 172: ...0H 1 OOOOH C000H 1 8000H 2 4 ATT ATT is the attenuation value ATT data is made up of 1 6 bit Bits DO and D1 5 are ignored and processed as 0 data Any data greater than 4OO0H is set to 4000H ATT setting value D15to DO Setting value 4DD0 I 0003 0002 0001 OOOOH 4000 I 0002 0002 0 000H X1 I I I XO 5 MODE MO De emphasis select H ON L OFF Noise shaping setting H normal noise shaping ON L when ATT x 1 40...

Page 173: ... D6 D6 D7 r7 17 MSB D7 D7 D8 r8 KO LSB D8 D8 D9 r9 K1 D9 D9 D10 no K2 D10 D10 D11 rll K3 DT1 D11 D12 r12 K4 D12 D12 D13 r13 K5 D13 D13 D14 r14 K6 Di4 014 MSB D15 r15 MSB K7 MSB D15 MSB L LO L H aO LSB MO LSB L1 a1 LSB a1 LSB a1 Ml L2 a2 a2 a2 M2 MSB L3 a3 a3 a3 L4 34 a4 a4 MSB L L L5 a5 aS L H L L6 a6 MSB a6 MSB L L H S L l H H H Items within angle brackets are fixed values Items marked are Don ca...

Page 174: ...int X OOOOH Transition point MUTE ATT operation 0 A OUT Full sca e siena V Mute area The time period during the ATT operation s rising and falling signal is equal to 23 22mS FS fs 44 1 kHz FS Full scale Continuous input of Input DATA occurs even during mule operations 170 ...

Page 175: ...al LRCK J is placed in the center of the synchronization window WINDOW ii LRCK rising signal position The synchronization circuit is controlled by clock signal CK1 txiffi Depending on external IC conditions LRCK is triggered by clock SCK fxt During synchronization the rising edge of LRCK is valid between the two points shown in the diagram below WCKO 1 SCK TjmruinjmiirLJirL tCKM WINDOW LRCKJ BCK L...

Page 176: ...SP DSP Block Diagram FIRl A D Lch Regis er A D Rch Register J L MO Selector K RAM MOP Register MPY P Register ADDER Ace Regstcr Clipaer RI Register R2 Register Ace LLn AOP Selector D A Lch Ren i D A Rch Register 3 FIR2 172 ...

Page 177: ...data 16 bit by register transfer command K RAM RAM K stores 2 s complement format 8 bit multiplication coefficients MOP Register Register MOP stores the 16 bit data instruction selected from the multiplication instruction command ADL ADR R1 Ace 1 6 MPY Executes each operation in sequence MOP 1 6 x K 8 P 20 P Register Register P for storing 16 bit x 8 bit length results of multiplication 20 bit AOP...

Page 178: ...ugend select bits 14 IS either Ace 22 R2 DAL or zero value is used as the augend The multiplication result P from the previous step is added to this and the addition result is latched to Ace 22 15 4 Adder 0 P 1 R2 P 1 Acc P 1 1 DAL P 3 Data I O instruction During a read cycle 17 H input data is latched to R1 During a write cycle 17 L either Ace or DAR are selected depending on the setting of 12 an...

Page 179: ..._ I 1 1 1 1 t k o VUTJUVJIRIITJITlTJlAT ii 8fs timing a r X u zcccGiaaxc t M 1 Bm BB7iT iiism r7fTwr iiniiiiiEEEriiQMiseescic nt i 1 l I i OUTPUT DA7A1 PATAI ATAL OATAA i r n c i r 3_ r n r J L n r L_r n_c i r zu m_Ji IX n_c ZL C n r 3_E ten i ZOCCCODCL _rznjjEG33333C33GGC32S CDZD0033 CCCCCGCCCL e EQOjCCC 2SES53IS30S33ISBE_ _a3DarocG3ccco3rcoc _ncccc xoax ico ijTiinjiniirumnrjuin iwirirjuTJUinAfij...

Page 180: ...mpling mode Frequency characteristics t Pass band 1 1 ftottoo __l__ Frequency characteristics 2 Stop band I 1 m i yfi B B J tfr j it 6 jji Quadrupled oversampling mode Frequency characteristics 1 Pass band Mfi Frequency characteristics 2 Stop band m TM I76 ...

Page 181: ...SONY I c o CD o D Q 177 ...

Page 182: ...SONY Package Outline Unit mm 44 p i n off Plastic 1 3 TYP J 0 16 l 5TW1 vent Mole 0 10 SOW NAME QFP 44P L102 J NAME XOFF04d 0300 2l JEOEC CODE 178 ...

Page 183: ...field processing using down sampling fs fs 2 Post processing with up sampling fs 2 fs Uses external DRAM either 4KX4 bit or 256Kx4 bif for delay control Delay amount for L and R channels can be set to a maximum of 64K delay samples Built in 32 bit equalizer register Digital de emphasis function 32K 44 1 K 48K Input Output format Input Two s complement MSB first LSB first 24 bit or 16 bit Output Tw...

Page 184: ...t pin Data is in two s complement format 4 BCKI I Serial bit clock input for serial input data 5 LRCKI Serial input output sampling frequency clock input pin When set High data is transferred when set Low R channel data L channel 6 Vss1 Ground pin 7 DATAO Serial data output pin Two s complement data format 8 BCKO O Bit clock output pin 64 slot 9 LRCKO Output tor sampling frequency clock s serial d...

Page 185: ...8 Vss2 Ground pin 29 A3 O External DRAM address output A3 30 A4 External DRAM address output A4 31 A5 External DRAM address output A5 32 A6 O External DRAM address output A6 33 A7 External DRAM address output A7 34 AS External DRAM address output A8 35 TEST1 I Test pin Normally set to Ground 36 TEST2 I Test pin Normally set to Ground 37 TEST3 I Test pin Normally set to Ground 38 TESTO Test pin 39 ...

Page 186: ... Input mode 0 8 Output voltage 1 H level VOH loH 2mA Vdd 0 5 V 4 L level Vol loL 2mA 0 4 Output voftage 2 H level Voh Output mode loH 2mA 2 4 V 5 L level Vol Output mode loL 1mA 0 4 Output voltage 3 H level Vom loH 2mA 2 4 V 6 L level Vot loL 1mA 0 4 Output voltage 4 H level I Voh loH 4mA 2 4 V 7 L level Vol lot 2mA 0 4 Input leak current 1 Ili Vi Vdd 0V 5 LlA 1 2 Input leak current 2 Ili Vi Vm 0V...

Page 187: ...I pulse width tWBI 100 nS DATAI setup time tcis 20 DATAI hold time tDIH 20 LRCKI setup time tLRIS 50 LRCK1 hold time tlRIH 50 PRG input base timing tPfl 100 nS PRGD setup time tPDS 50 PRGD hold time tPDH 50 PRGL rise time u 200 PRGL tall time bL 200 PRGL pulse width tWLT X 1 fXT 8 T PRGL pulse interval 111 512 t OVF defined time tov 40 nS Timing specified level O SVdd tn 0 1VoD trL 0 9Voo I 183 ...

Page 188: ...SONY CXDZT010 DATA Input BCKI DATAI LRCKI Don t care PRG Input Output PRGD zx X J PRGL OVF 1 j A h T J I PR t R PP CL t y Timing specified level 0 5Vtoo tfl_ 0 1Voo trl_ 0 9V D 184 ...

Page 189: ...T nS CAS pre charge time tcp T 12 T CAS pulse width tCAS 2 x 12 2t Low address hold time tRAH T 20 T nS Column address setup time Use t 20 T Column address hold time i x 18 T Read data setup time tRDS 20 nS Read data hold time tRDH 5 Write data hold time twDH T 18 T T 1 1 fXT 512fs CL 30pF Timing specified level 2 4V 0 8V I 185 ...

Page 190: ...SONY CXC2701Q III It 0 V CO 3 O a f 1 a 4 a 5 U xTi v1 _IxtS v i i t k m r T X K i i X v o ISO ...

Page 191: ...tBUt Rod URoa I I th order FIR IIRia m llth orier FIB l 2fs fs DSP PRG I F 1 o uCOM O RAM I Asterisk items represent data transferred from the microprocessor EQ Equalization coefficient DSP DSP program coefficient IIRoa URob IIRia IIRib MR filter coefficients mO ml mixing coefficient 10 11 12 coefficients All above values for current charging times are undefined 187 ...

Page 192: ...erred to the internal shift register activated by the rising edge signal PRGL When serial data PRGD is input to the shift register data Is globally latched by the gate pulse active when set low Concurrently with the rising edge a processing request is sent internally to thelC The transfer format and timing are shown below S 1 bit When set Low DSP transfers active when set High non DSP transfers L ...

Page 193: ...s r15 MSB K7 Lo L H Li aO LSB aO LSB Ls a1 a1 b a2 a2 L a3 a3 L5 a4 a4 u a5 MSB a5 MSB s L L K RAM Do DO Di D1 Dj D2 Da D3 D D4 Ds D5 D D6 D7 D7 D D8 Do D9 Dto D10 Dii D11 Dl2 D12 Dii D13 DT4 D14 Dis D15 Dia D16 DlT D17 Die D18 Dm D19 Lo aO LSB Li a1 La a2 La a3 L4 a4 Ls a5 MSB Le L S H MODE Do MO LSB Di M1 Da M2 Ds M3 D4 M4 Ds M5 De M6 D7 M7 MSB Lo L Li L Ls H S H I Items in brackets are characte...

Page 194: ...SONY CXD27CTG h E 4 i a 3 o 3 DC a Il ii o 1 O c T r T u o o 1 1 5 1 o it J M a UJ a a i 7 190 ...

Page 195: ...i Bi 2 F2 1 1 1 PG11 R PEAKING a PGio L 1 Bi 1 Fi 1 1 PGz R PGoc L PEAKING 1 Bo Fo 1 1 1 X SGit R SHELVING X SGio L 1 X PHi 1 X Li 1 1 X SGoi R SHELVING X SGoo L 1 X PHo X Lo 1 1 1 1 1 rx fIR B ba 1 bi bi X X bo 1 1 1 34 IIR A aa i at at X X ao 1 1 X X ____ 1 1 bi R LEVEL bo L 1 In R ho L 1 X X lo 1 1 mii R MIX mio L o 1 moi R moo L I 43W 191 ...

Page 196: ...asls ON De emphasis OFF Ms DC CUT Ms Settings 1 DC CUT ON DC CUT OFF M DSP M Settings 1 DSP operation ON DSP operation OFF Mr EQ Mj Settings 1 EQ operation ON EQ operation OFF Mr TEST MODE Mi Settings 1 Test mode Normal mode Mi 1M 256 Mi Settings 1M bit external DRAM for DSP use 256K bit external DRAM for DSP use Mo Not used 192 ...

Page 197: ...SONY CXD270 Q DSP Explanation DSP Section Block Diagram I 193 ...

Page 198: ...ter for storing accepted data 1 6 bit during the I O process R1 Register for storing R1 register data 16 bit by transfer instructions R2 RAM for storing two s complement format multiplication coefficient 8 bit K Register for storing the multiplication data 16 bit selected from the various multiplication instructions ADL ADR R1 Ace 16 MOP Executes each operation in sequence MOP 1 6 xK 8 P 20 Regist...

Page 199: ... on the augend select bits 14 15 one of the data from Ace 22 R2 DAL or Null is selected as the augend The multiplication resuit of pre step P is added to this augend and the result latched to Ace 22 15 14 Adder 0 P 1 R2 P 1 Acc P 1 1 DAL P 3 Data input output instructions During Read time 17 is High the Input data is latched to R1 During Write time 17 is Low either Ace or DAR is selected 12 13 and...

Page 200: ...ve addresses m to re ais to ao bis to bo rw to ro Carry over is ignored In the case of 256K DRAMs in order for the upper 2 bits ais and an not to be used among relative addressing addresses ris and ri4 are made invalid IM D RAM Pin Name Add A8 A7 A6 AS A4 A3 A2 A1 AO Row R ae a7 ae as 34 as 32 ai ao Column Co ais an at a air an aio at Cj 1 Cz 1 C3 1 1 256K D RAM Fln Name Add v A3 A7 A6 A5 A4 A3 A2...

Page 201: ...mes during 2 fs is calculated as follows _2_ v _J1_ 4mS 8mS fs N N 256 128 fs 512 fs 32kHz fs 44 1kHz fs 48kHz NI4 0 N 2 9 NS2 7 In order that all low address refresh is completed within the defined time so that all low address delay periods are equal to N time accesses leading be sure to set relative address rrs to ro Example When N 4 times set following addresses 256K D RAM OOOOh 0040k OOSOh OOC...

Page 202: ... 1 L i i Ifr l z_ IjmQce l jdjs l I f l C C l il DATAI H6I J i J r fc i I MOCEI H 1DER H DATA I 241 T t j n C DATA t 16 t TH 16 p t I mqd h IDIR V ATA 24 DATAI L16S 1 ll t i 1 i B i i I I t 1 h L i i F e t i i DATA Output Timing GCXQ JWLlinJUWlAIWdTJVi od h B52 BS1 H H BS2 S5 1 H 1 DATAO 6 2 B51 B 2 BSl i_ odsr r BS2 K BSl H DATAO es i BS2 BS I L 9 2 BS 1 1 r rh 34 bU 1 M L H 1 1 L th 0 Mi 1 1 K c...

Page 203: ...UUi jWJiTrjwuinnnnawjuLTnjinnnJui Post re synC Durino power L supply ON TT A IDT ieT h rH 6t C l I set WINDOW width i _ Operation during Power Supply ON OFF Vdd INIT DA AI Out out timing clock 7 Re sync n_ i DATAO XIN Undefined PRG initial value input interval nt mt j Undefined 1 Ci_ 199 ...

Page 204: ...circuits shown are typical examples illustrating I he operation ol the devices Sony cannot assume responsibility lor any problems arising out ot Ihe use ol these circuits or lor any infringement of third party patent and other right due to same 200 ...

Page 205: ... CX D2 T0 10 Package Outline Unit mm 4 4 p i n QFP Plastic l ig DiB M o i 0 15 o oS 0 0 15 I to 1 s as 5 C 4 H 1 7 5 o i 5 Q 1 C C5 ie o i2i H SONY NAME QFP d4P L01 EIAJ NAME QFP0a4 P iai4 A JEDEC CODE 201 ...

Page 206: ......

Page 207: ...Digital Audio Interface IC ...

Page 208: ...4 Digital Audio Interface IC Type Functions Page CXD1211P Digital audio data modulation Transmission 205 204 ...

Page 209: ...Fs 192Fs 256Fs and 384Fs can be selected for the master clock Dual inputs are provided for each of Digital Au dio Data and Channel Status Data C2 bit Structure Silicon gate CMOS IC Application Maximum Ratings Ta 25 C Supply voltage Vdd Vss 0 5 to 7 0 V Input voltage Vi Vss 0 5 to Vdd 0 5 V Output voltage Vo Vss 0 5 to Vdd 0 5 V Operating temperature Topi 20 to 75 C Storage temperature T ta 55 to 1...

Page 210: ...SONY u o DO O B UJ Ct Q w h X 206 ...

Page 211: ...g Preset input of channel status data bit 9 12 CIO Preset input of channel status data bit 10 13 MUTE Muting input H Only the audio data on TX will be 0 14 EXTAL Clock input The frequency is selected from 128Fs 192Fs 256Fs 384Fs at CKS1 pin 61 and CKS2 pin 81 15 TX Output of transmitting data converted in digital audio interface format 16 ABSL Selection input of DATA pin 21 DATB pin 3 and C2 pin 2...

Page 212: ...0 4 V Input voltage High level Vim 2 4 V Low level Vn 0 8 V Input leak current In Vi 0V to Vbo 10 10 M I O capacitances Ta 25 C Voo Vi OV fM 1MHz Item Symbol Mm Typ Max Unit Inputs C 9 pF Outputs Cour 9 pF AC characteristics Item Symbol Min Typ Max Unit LRCK to 3CK setup time tou 50 ns LRCK to BCK hold time llHO 50 ns DATA DATS to BCK set up time twu 50 ns DATAflDATB to BCK hold time Tann 50 ns BC...

Page 213: ... permits the following 1 bits to be set Bit 1 2 3 8 9 1 0 24 2 5 28 and 29 Set these bits in parallel at the respective inputs With these bits the following items can be determined a Digital data Audio data b Emphasis On Off c Digital copy enable disable d Category codes up to 8 kinds e Sampling frequency 44 1 kHz 48 kHz 32 kHz f Clock accuracy level I II I1I Dual Input selection This IC is equipp...

Page 214: ...frequencies at CK52 ipin 6 CKS2 pin8 as shown below Table 1 Clock frequency CKS1 CKS2 EXTAL frequency 128Fs 1 192Fs 1 256Fs 1 1 384Fs When inputting 192Fs to EXTAL note that the output at TX may have jitters depending on the clock duty See Fig 1 TX Fig 1 TX when inputting 192Fs clock to EXTAL 210 ...

Page 215: ...SONY 0J r O C 3 a n CM I DC si J m m m t 5 w 5 Q Q S t t U3 5 211 ...

Page 216: ...ircuit Sub audio data digital copy enablef disable TV audio data digital copy enable disable ABSL 16 DATA DATA B C2A C2B TX 15 6 144MHz Connection example with Toshiba TM4218N audio signal processing IC for B S Tuner 212 ...

Page 217: ...HP Package Outline Unit mm 2 8 p i n DIP Plastic 600mil 4 0g is 15 n n n n n n n n n n n n n n 3 5 5 11 41 Q uuuuuuuuuuuufu 2 5 4 o 35 5 5 0 15 14 WmwmwH jf 02 5 i SONY NAME DIP 2BP 022 EIAJ NAME 5 uEDEC ccqe 213 ...

Page 218: ......

Page 219: ...eting Division Semiconductor Marketing Group 4 10 18 Takanawa Minatoku Tokyo 108 Japan a 03 3448 3426 Fax 03 3448 7493 Sony Semiconductor Integrated Circuit Data Book 1992 Apr 1st Edition Edited and Published by Application Engineering Division Semiconductor Group Sony Corporation Printed in Japan at HIKARI SHASHIN PRINTING CO LTD Copyright 1992 by Sony Corporation DE92231 HP ...

Page 220: ...Sony Semiconductor o 9i 1 ...

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