Sony Cineza VPL-HS60, Service Manual

Page: 111 / 138

6-21
VPL-HS60/HS51A
6-21
C C
C (1/19) 24LC21AT/SN (IC100)
5
7
6
8
4
1 2 3
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
H/V
GENERATOR
SENSE AMP
R/W CONTROL
YDEC
SDA
VCLK
SCL
VCC
VSS
NC NC NC
C (1/19, 31/19) SN74LV4052APWR (IC102, IC401)
13
10
9
6
12
1-COM
A
B
INH
1Y0
14
1Y1
15
1Y2
11 1Y3
1 2Y0
5
2Y1
2 2Y2
4 2Y3
3 2-COM
C (2/19) LC4032V-75TN48C-DLY2 (IC200)
16
16
36
16
16
36
I/O
BLOCK
ORP
GENERIC
LOGIC
BLOCK
I/O
BLOCK
ORP
GENERIC
LOGIC
BLOCK
·
·
·
16
16
36
6
16
16
36
I/O
BLOCK
ORP
43
CLK0/I
18
CLK1/I
19
CLK2/I
42
CLK3/I
44
GOE0
11
TCK
25
TMS TDI
35
TDO
30
V
CCO1
29
GND
41
GOE1
20
24
·
26
28
·
31
34
·
38
41
V
CC
GND GND
5 1
V
CCO0
GENERIC
LOGIC
BLOCK
I/O
BLOCK
I/O BANK 0 I/O BANK 1
ORP
GENERIC
LOGIC
BLOCK
GLIBAL
ROUTING
POOL
2
4
·
7
10
·
14
17
·
45
48
·
·
·
12 · 36 13 · 37
C (2/19) ST72T631K4M1-201 (IC201)
OSCIN
PA [7:0]
(8 BITS)
PB [7:0]
(8 BITS)
PC [7:0]
(3 BITS)
USBDP
USBDM
USBVCC
OSCOUT
VDD
VSS
RESET
Vpp/TEST
VDDA
VSSA
OSCILLATOR
WATCH DOG
LVD
I
2
C*
PORT A
PORT B
PORT C
ADC
16-BIT TIMER
CONTROL
USB DMA
USB SIE
PROGRAM
MEMORY
(4K/8K/16K BYTES)
POWER
SUPPLY
8-BIT CORE
ALU
SCI*
(UART)
RAM
(256/512 BYTES)
INTERNAL
CLOCK
OSC/3
OSC/4 or OSC/2
(FOR USB)
ADDRESS AND D
A
T
A
B
U
S
10
11
.
.
13
18
5
7
31
33
19
24
.
.
28
29
3
2
1
8
12
34
30
4
*Not on all products (refer to Table 1 : Device Summary)
C (3/19, 17/19) BR24L02F-WE2 (IC400, IC1807)
1
2
3
4
7
8
6
5
HIGH VOLTAGE
RAISING CIRCUIT
POWER VOLTAGE
DETECTOR
SLAVE WORD
ADDRESS REGISTER
DATA
REGISTER
ADDRESS
DECODER
1K BIT EEPROM ARRAY
CONTROL
CIRCUIT
7BIT
7BIT
8BIT
ACK
START STOP
A0
A1
A2
GND
VCC
WP
SCL
SDA
C (3/19) SII9993CTG100 (IC403)
32
71
9 8
76
12
77
81
83
·
84
86
·
87
91
·
92
96
·
97
75
74
26
27
31
30
29
35
33
7
12
15
34
45
36
39
·
42
44
·
48
55
·
58
63
·
68
70
I 2 C
SUB
I 2 C
SUB
REGISTERS
____________
CONFIGURATION
LOGIC BLOCK
HDCP
KEYS
EEPROM
HDCP
DECRYPHON
ENGIN
AUX DATA
LOGIC
BLOCK
AUDIO
DATA
DECODE
LOGIC
BLOCK
VIDEO
COLOR
SPACE
CONVERTER
UP/DOWN
SAMPLING
XDR
MASK
MODE
CONTROL
PANEL LINK
TMDS
DIGITAL
CORE
MCLK
GEN
VIDEO
DAC
CSDA
CSCL
MCLKOUT
MCLKIN
SCK
WS
SDO
SPDIF
DE
HSYNC
VSYNC
ODCK
Q0-Q23
AnRPr
AnGY
AnBPb
CCMP
RESET
RESET
DSDA
DSCL
EXT-RES
RXC + , _
RXD + , _
RX1 + , _
RX2 + , _
INT
30
24