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CDP-XE530
— 27 —
— 28 —
6-10. IC PINFUNCTIONS
•
IC101 DIGIT
AL SIGNAL PR
OCESSOR (CXD2585Q)(BD boar
•
A
b
b
re
viation
GFS : Guarded Frame Sync
•
A
bbr
eviation
EFM
: Eight to F
ourteen Modulation
PLL
: Phase Lock
ed Loop
D
VDD
XRST
MUTE
DA
T
A
XLA
T
CLOK
SENS
SCLK
A
TSK
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
CM4
WDCK
D
VSS
COUT
MIRR
DFCT
FOK
PWMI
LOCK
MDP
SSTP
FST
O
D
V
DD1
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
D
VSS1
TEST
TES1
VC
FE
SE
–
I
I
I
I
I
O
I
I
O
O
O
O
O
O
O
O
–
I/O
I/O
I/O
I/O
I
I/O
O
I
O
–
O
O
O
O
O
O
–
I
I
I
I
I
Dig
System reset
Muting input “H” : mute
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
SENS signal output to CPU
SENS serial data read-out clock input
Input pin for anti-shock (Connected to ground)
WFCK output (Not used)
Not used
Not used
Not used
Not used
Sub-code sync output
4.2336 MHz output (Not used)
W
o
rd
c
loc
k output (ƒ = 2Fs)
Digital ground
Numbers of track counted signal input/output (Not used)
Mirror signal input/output (Not used)
Defect signal input/output (Not used)
F
ocus OK input/output (Not used)
Spindle motor e
xter
nal contr
ol input (Connected to ground)
GFS is sampled by 460 Hz. H when GFS is H (Not used)
Output to control spindle motor serv
o
Input signal to detect disc inner most track
2/3 di
vider output of pin 71 (Not used)
Dig
ital po
wer suppl
y
Sled dr
iv
e output
Sled dr
iv
e output
T
rac
king dr
iv
e output
T
rac
king dr
iv
e output
F
ocus dri
v
e output
F
ocus dri
v
e output
Digital ground
TEST pin connected normally to ground
TEST pin connected normally to ground
Center v
olta
g
e input pin
F
ocus er
ror signal input
Sled error signal input
Pin No.
Pin Name
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin No.
Pin Name
I/O
Function
TE
CE
RFDC
ADIO
A
VSS0
IGEN
A
VDD0
ASY
O
ASYI
RF
A
C
A
VSS1
CL
TV
FILO
FILI
PCO
A
VDD1
BIAS
VCTL
V16M
VPCO
DV
D
D
2
ASYE
MD2
DOUT
LRCK
PCMD
BCLK
EMPH
XTSL
D
VSS2
XT
AI
XT
A
O
SOUT
SOCK
XOL
T
SQSO
SQCK
SCSY
SBSO
EXCK
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I
I
I
O
–
I
–
O
I
I
–
I
O
I
O
–
I
I
I/O
O
–
I
I
O
O
O
O
O
I
–
I
O
O
O
O
O
I
I
O
I
T
rac
king error signal input
Center ser
v
o
analog input
RF signal input
T
est pin (Not used)
Analog ground
Stabiliz
ed current input for oper
a
tional amplif
iers
Analo
g po
wer suppl
y
EFM full swing output
Asymmetry compara
te v
olta
g
e input
EFM signal input
Analog ground
Control v
olta
g
e input for master
VCO1
Filter output for master PLL
Filter input for master PLL
Char
g
e-pump output for master PLL
Analo
g po
wer suppl
y
Asymmetry circuit constant current input
VCO2 control v
olta
g
e input for wide band EFM PLL (Connected to
VDD)
VCO2 oscillator input/output for wide band EFM PLL (Not used)
Char
g
e-pump output for wide band EFM PLL (Not used)
Dig
ital po
w
er suppl
y
Asymmetry circuit ON/OFF input
“L” OFF
,
“H” : ON (Connected to
VDD)
Dig
ital-out ON/OFF control input (Connected to
VDD)
Digital-out output pin
D/A interface LR c
loc
k output (ƒ = Fs)
D/A interface serial da
ta output
D/A interface bit cloc
k output
Playback disc output in emphasis mode (Not used)
X'tal selection input (Connected to ground)
Digital ground
X'tal oscillator circuit input
X'tal oscillator circuit output (Not used)
Serial da
ta output in ser
v
o
b
lock (Not used)
Serial da
ta r
ead c
loc
k output in ser
v
o
block (Not used)
Serial da
ta latch output in serv
o bloc
k (Not used)
Sub-Q 80-bit and PCM peak le
v
el data output (CD te
xt data output)
Clock input for SQSO read-out
Connected to ground
Sub-P through Sub-W serial output (Not used)
Clock input for SBSO read-out (Connected to ground)
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