8
D-EJ750/EJ751/EJ753/EJ755/EJ756CK/EJ758CK
Pin No.
Pin name
I/O
Description
SECTION 5
DIAGRAMS
5-1. EXPLANATION OF IC TERMINALS
IC601 (SYSTEM CONTROL) CXD3029R (DSP IC)
1
XRAM
O
DRAM low address strobe signal outut.
2
XWE
O
DRAM data input enable signal output.
3 to 6
D0 to 3
I/O
DRAM data bus 0 to 3.
7
DCLK
O
Not used (OPEN).
8
DCKE
O
Not used (OPEN).
9
XCAS
O
DRAM column address storobe signal output.
10
WFCK
O
Not used (OPEN).
11 to 13
A7 to 9
O
DRAM address 7 to 9.
14
DVss
–
Ground terminal for DRAM interface.
15 to 17
A4 to 6
O
DRAM addres 4 to 6.
18
XRDE
I/O
Not used (OPEN).
19
V
DD
0
–
Power supply for digital.
20
CLOCK
I
Serial data transfer clock input.
21
SDTO
I
Serial data input.
22
SENS
O
SENS output.
23
XLAT
I
Latch input.
24
XSOE
I
CPU serial data output enable signal input.
25
SYSM
I
Mute input. “H” : MUTE
26
WDCK
O
Word clock output.
27
SCOR
O
SCOR output.
28
XRST
I
Reset terminal.
29
PWMI
I
Spindle moter external contorol input.
30
XQOK
I/O
Not used (OPEN).
31
XWER
I/O
DRAM write enable signal input.
32
R4M
O
System clock output.
33
Vss0
–
Digital ground terminal.
34
SQCK
I
Clock input for SQSO read out.
35
SCLK
I
Clock input for SENS serial date read out.
36
SQSO
O
Not used (OPEN).
37
XEMP
O
Not used (OPEN).
Not used (OPEN).
Not used (OPEN).
Not used (Fixed at “L”).
Not used (Fixed at “L”).
Ground terminal for headphones.
Headphone output (L-CH).
Headphone output (R-CH)..
Power supply terminal for headphones.
Power supply terminal for master clock.
Master clock input.
48
XTAO
O
Master clock output.
49
XVss
–
Ground terminal for master clock.
50
AV
DD
1
–
Power supply terminal for analog.
51
AOUT1
O
Line out (L-CH).
52
VREFL
O
VREF terminal (L-CH).
53
AVss1
–
Ground terminal for analog.
54
AVss2
–
Ground terminal for analog.
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