Chassis
RB2G,
HE-L
136
Chassis
RB2G,
HE-L
A BOARD SCHEMATIC DIAGRAM (6 OF 24)
FIF_RND_DAT[6]
FIF_RND_DAT[5]
FIF_RND_DAT[4]
FIF_RND_DAT[7]
FIF_RND_DAT[3]
FIF_RND_DAT[2]
FIF_RND_DAT[1]
FIF_RND_DAT[0]
FIF_RND_DAT[4]
FIF_RND_DAT[0]
FIF_RND_DAT[1]
FIF_RND_WE_X
FIF_RND_DAT[3]
FIF_RND_WP_X
FIF_RND_ALE
FIF_RND_CLE
FIF_RND_DAT[2]
FIF_RND_RE_X
FIF_RND_RB
FIF_RND_DAT[6]
FIF_RND_DAT[5]
FIF_RND_DAT[7]
FIF_RND_WP_X
FIF_RND_WE_X
FIF_RND_CE_X
FIF_RND_RB
FIF_RND_RB
FIF_RND_RE_X
FIF_RND_ALE
FIF_RND_CLE
FIF_RND_CE_X
C1013
0.1
RB1001
68
RB1000
68
CL1009
CL1010
CL1008
CL1012
C1014
XX
0
R1043
CL1014
+3.3V_NAND
C1007
XX
0
R1042
CL1013
+3.3V_NAND
GND_D
0
R1037
CL1011
0
R1038
CL1015
47
R1019
XX
R1039
0
R1041
CL1039
0
R1040
CL1038
CL1040
CL1042
CL1044
C1015
XX
STBY_+3.3V
CL1043
CL1041
CL1017
CL1018
CL1048
CL1016
CL1047
CL1046
CL1020
CL1045
C1012
0.1
RB1008
68
2
1
4
3
6
5
8
7
+3.3V_NAND
CL1051
47
R1020
RB1007
68
2
1
4
3
6
5
8
7
100k
R1003
CL1019
CL1049
CL1050
GND_D
CL1052
XX
R1012
CL1022
C1000
0.1
CL1021
NAND1_PWR
005:9B
10k
R1008
1005
47
R1022
XX
R1010
GND_D
GND_D
GND_D
SPID_DI
018:6H;018:11I
SPIC_DI
018:6G;018:11H
STBY_+3.3V
+3.3V_MAIN
BAX_L BOARD
FLASH MEMORY INTERFACE
ALL resistors are in ohms,W unless otherwise noted.
ALL capacitors are in uF(p:pF)unless otherwise noted.
2013/12/05
00:16
RB2_BAX_L_PP3_041213.cir/006.sht
5004103813
RB2
6/18
To PCB System
XX
R1000
XX
R1001
+3.3V_NAND
47k
R1027
RB1002
47K
GND_D
GND_D
+3.3V_NAND
+3.3V_NAND
1k
R1026
47k
R1028
IC1000
TC58NVG3S0FTAI0B4Q
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO0
IO1
IO2
IO3
NC
NC
NC
VSS
VCC
NC
NC
NC
IO4
IO5
IO6
IO7
NC
NC
NC
NC
STBY_GPIO_19 005:12C
GPIO_11
004:7F
GPIO_3
004:7E
GPIO_4
004:7E
GPIO_9
004:7E
GPIO_10
004:7E
GPIO_15
004:7F
GPIO_16
004:7F
GPIO_14
004:7F
GPIO_35
004:7G
GPIO_44
004:7G
RB1009 47
2
1
4
3
6
5
8
7
GND_D
+3.3V_MAIN
C1006
XX
C1002
XX
C1003
XX
C1016
XX
C1017
XX
C1018
XX
C1019
XX
*IC9000
CXD4748GB
AB18
VDD_NAND
AB19
VDD_NAND
AC18
VDD_NAND
AC19
VDD_NAND
H18
VDD_NAND_STBY
AG30
RND_IO_0/RND_IO_0
AG29
RND_IO_1/RND_IO_1
AF28
RND_IO_2/RND_IO_2
AH30
RND_IO_3/RND_IO_3
AG28
RND_IO_4/RND_IO_4
AH29
RND_IO_5/RND_IO_5
AJ30
RND_IO_6/RND_IO_6
AH28
RND_IO_7/RND_IO_7
AF27
GPIO_3/RND_IO_8
AJ27
GPIO_4/RND_IO_9
AK27
GPIO_9/RND_IO_10
AH26
GPIO_10/RND_IO_11
AJ26
GPIO_11/RND_IO_12
AK26
GPIO_14/RND_IO_13
AG26
GPIO_15/RND_IO_14
AF26
GPIO_16/RND_IO_15
AH27
RND_RE_X/RND_RE_X
AJ29
RND_WE_X/RND_WE_X
AK28
RND_RB/RND_RB
AJ28
RND_ALE/RND_ALE
AK29
RND_CLE/RND_CLE
AE26
GPIO_35/RND_TEST_0
AE27
SYNC_4K2K/RND_TEST_1/GPIO_44
A24
STBY_RND_CE0_X/STBY_RND_CE0_X
B17
STBY_SPIA_DO/STBY_GPIO_19/STBY_RND_CE1_X
B24
STBY_RND_WP_X/STBY_RND_WP_X
Q1000
PDTC144EU
Q1001
PMV32UP
FET SW for RawNAND
40m ohm_@Vgs=-2.5V
I = 1A
RawNAND_0_lower
[Strap][Flash Construction Settings]
SPID_DI:SPIC_DI
=STRAP_G[14:13]
=11:
=10:
=01:
=00:
"Boot"
RawNAND
RawNAND
RawNAND
RawNAND
"Bit Width"
8x2
16x1
8x2
8x1
Current Setting: [ALL] 00
For Micron
25:NC -> GND
48:NC -> GND
34:NC -> VCC
39:NC -> VCC
WP and CE are STBY domain line.
Each R is put near STBY domain.
Integrate PullUp/Down R to RB
for cost down
Integrate Dumping R to RB
for cost down
For upper NAND data line
For cascade toporogy
PLEASE PUT B-side
2013/07/05 18:18
[ SOC ]
┌────────┬────────┬────────┐
│
│
60
│
60AVS
│
├────────┼────────┼────────┤
│
IC9000
│
CXD4748GB
│
CXD4748GB-1
│
└────────┴────────┴────────┘
1234567
42
43
44
45
46
47
48
41
40
39
38
37
3
6
35
34
33
16
15
14
13
12
11
10
98
32
31
30
29
28
2
7
2
6
25
17
18
19
20
21
2
2
2
3
24
FIF
S
DESCRIPTION
A
4
H
11
MODEL
B
5
I
12
ORIGINAL
C
6
J
13
SHEET
D
7
K
14
1
E
8
L
15
2
F
9
PART NO.
16
3
G
10
