Sony BDKP-N1001, Maintenance Manual

Page: 52 / 110

3-4
BDX-N1000
IC
CLOCK
SYNC
PECL
TTL
FRAMER
SHIFTER
DECODER
REGISTER
DECODER
OUTPUT
REGISTER
A/
B
INA
+
RF
INA _
MODE
7
BISTEN
4
25
23
27
28
1
2
3
5
INB(INB + )
SI(INB _ )
SO
REFCLK
TEST
LOGIC
Q0 - Q7
(Q
B
- Q
H
)
RDY
10 - 18 19 7 22
SC/
D
(Q
A
)
CKR
DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I
I
I
I
I
—
O
—
—
O
O
O
O
O
O
O
O
O
O
—
—
O
O
—
I
I
I
I
INA _
INA +
A/
B
BISTEN
RF
GND
RDY
GND
V
CC
RVS(Q
J
)
Q7(Q
H
)
Q6(Q
G
)
Q5(Q
F
)
Q4(Q
I
)
Q3(Q
E
)
Q2(Q
D
)
Q1(Q
C
)
Q0(Q
B
)
SC/
D
(Q
A
)
GND
V
CC
CKR
SO
V
CC
REFCLK
MODE
SI(INB _ )
SI(INB + )
PIN
NO.
PIN
NO.
I/O I/O SIGNAL SIGNAL
5
6
7
8
9
10
11
25
24
23
22
21
20
19
12 13 14 15 16 17 18
4 3 2 1 28 27 26
RECEIVER
—TOP VIEW—
INPUTS
A/
B
BISTEN
INA + , INA _
INB + , INB _
MODE
REFCLK
RF
SI
OUTPUTS
CKR
Q0(Q
B
)-Q7(Q
H
)
RDY
RVS(Q
J
)
SC/
D
(Q
A
)
SO
: SERIAL DATA INPUT SELECT
: BUILT-IN SELF-TEST ENABLE
: SERIAL DATA A
: SERIAL DATA B
: DECODER MODE SELECT
: REFERENCE CHECK
: REFRAME ENABLE
: STATUS
: CLOCK READ
: PARALLEL DATA
: DATA OUTPUT READY
: RECEIVED VIOLATION SYMBOL
: SPECIAL CHARACTER/DATA SELECT
: STATUS
CY7B923-JC (CYPRESS)
5
6
7
8
9
10
11
26
27
1
28
2
3
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
O
O
O
—
I
—
I
O
—
I
I
I
I
I
I
I
I
I
I
—
I
—
I
I
I
O
O
O
OUT B _
OUT C _
OUT C +
V
DD
BISTEN
GND
MODE
RP
V
DD
SVS(D
J
)
D7(D
H
)
D6(D
G
)
D5(D
F
)
D4(D
I
)
D3(D
E
)
D2(D
D
)
D1(D
C
)
D0(D
B
)
SC/D(D
A
)
GND
CKW
V
DD
ENA
ENN
FOTO
OUT A _
OUT A +
OUT B
+
PIN
NO.
PIN
NO.
I/O I/O SIGNAL SIGNAL
18
17
16
15
14
13
12
11
10
19
5
7
21
23
24
25
D0(D
B
)
D1(D
C
)
D2(D
D
)
D3(D
E
)
D4(D
I
)
D5(D
F
)
D6(D
G
)
D7(D
H
)
SVS(D
J
)
SC/D(D
A
)
BISTEN
MODE
CKW
ENA
ENN
FOTO
OUT A _
OUT A +
OUT B _
OUT B +
OUT C _
OUT C +
RP
25
24
23
22
21
20
19
INPUTS
BISTEN
CKW
D0 - D7
ENA
ENN
FOTO
MODE
SC/D (DA)
SVS (DJ)
OUTPUTS
OUT A + , OUT A _
OUT B + , OUT B _
OUT C + , OUT C _
RP
: BUILT-IN SELF TEST ENABLE
: CLOCK WRITE
: PARALLEL DATA
: ENABLE PARALLEL DATA
: ENABLE NEXT PARALLEL DATA
: FIBER OPTICAL TRANSMITTER OFF
: ENCODER MODE SELECT
: SPECIAL CHARACTER/DATA SELECT
: SEND VIOLATION SYMBOL
: DIFFERENTIAL SERIAL DATA
: DIFFERENTIAL SERIAL DATA
: DIFFERENTIAL SERIAL DATA
: READ PULSE
4 3 2 1 28 27 26
12 13 14 15 16 17 18
BIC-MOS TRANSMITTER
—TOP VIEW—
CY7B933-JC (CYPRESS)
D7
28
CK
CLS
12
11
RST
1
D6
D5
D4
D3
D2
D1
D0
27
26
25
24
23
20
19
3 4 5 6 10 13 17 18 2
A0 A1 A2 A3 A4
ASCII
CODE
(7 BITS)
COLUMN
DATA
DISPLAY
0 1 2 3 4 5 6 7
MUX RATE BLINK RATE
TIMING AND CONTROL LOGIC
WR CE RD FL
CONTROL
WORD
DECODE
LOGIC
ROW DECODER
MAIN
SUB
LATCHES
DIGIT
0 TO 7
COLUMN
DRIVERS
FOR
DIGIT
0 TO 7
ROW CONTROL LOGIC
AND
ROW DRIVERS
OSC
÷32
USER RAM
MEMORY
(8 x BITS)
ROM
128 x 7 BITS
ASCII
CHARACTER
DECODER
(4.48 K BITS)
RAM
16 x 7 BITS
USER’S
CHARACTER
DECODER
(4.48 K BITS)
FLASH RAM
(8 x BITS)
ADDRESS DECODER
RAM READ LOGIC
CONTROL WORD
COLUMN DECODER
LATCHES
PAGE RAM
÷7 ÷128
HDSP-2111 (HP)
8-COLUMN DISPLAY (5
x
7-DOT) WITH DECODER AND DRIVER
—TOP VIEW—
28 27 26 25 24 23 20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I
I
I
I
I
I
I
I
I
I
I
I
I
—
—
—
I
I
I
I
—
—
I
I
I
I
I
I
RST
FL
A0
A1
A2
A3
STR
STR
STR
A4
CLS
CK
WR
V
DD
GND
GND
CE
RD
D0
D1
—
—
D2
D3
D4
D5
D6
D7
PIN
NO.
PIN
NO.
I/O I/O SIGNAL SIGNAL
INPUTS
A0 - A4
CE
CK
CLS
D0 - D7
FL
RD
RST
STR
WR
: ADDRESS
: CHIP ENABLE
: CLOCK
: CLOCK SELECT
: DATA
: FLASH RAM
: READ
: RESET
: SUBSTR BIAS
: WRITE
MODE
BISTEN
FOTO
SHIFTER
27
26
28
1
3
2
8
ENCODER
ENABLE
INPUT
REGISTER
CLOCK
GENERATOR
TEST
LOGIC
7
5
25
SVS(D
J
)
SC/D(D
A
)
D0(D
B
)
D1(D
C
)
D2(D
D
)
D3(D
E
)
D4(D
I
)
D5(D
F
)
D6(D
G
)
D7(D
H
)
10
19
18
17
16
15
14
13
12
11
CKW
ENA
ENN
21
23
24
OUT A +
OUT A _
OUT B +
OUT B _
OUT C
+
OUT C _
RP