SONIX SN8P26L00 Series User Manual Download Page 24

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SN8P26L00 Series

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 24

Preliminary Version 0.2

2.1.3 DATA MEMORY (RAM)

)

240 X 8-bit RAM

Address

RAM location

000h

“
“

Bank 0

“
“
“

02Fh

General purpose area

080h

“

80h~FFh of Bank 0 store system
registers (128 bytes).

“
“
“
“

System register

BANK 0

0FFh

End of bank 0 area

100h Bank

“
“
“
“
“

BANK 1

16Fh

General purpose area

Summary of Contents for SN8P26L00 Series

Page 1: ...not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application...

Page 2: ...8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 2 Preliminary Version 0 2 AMENDMENT HISTORY Version Date Description VER 0 1 Dec 2006 First Issue VER 0 2 Mar 2007 1 Add SN8P26L321 pin assignment...

Page 3: ...2 1 1 4 JUMP TABLE DESCRIPTION 20 2 1 1 5 CHECKSUM CALCULATION 22 2 1 2 CODE OPTION TABLE 23 2 1 3 DATA MEMORY RAM 24 2 1 4 SYSTEM REGISTER 25 2 1 4 1 SYSTEM REGISTER TABLE 25 2 1 4 2 SYSTEM REGISTER...

Page 4: ...Bias Reset Circuit 48 3 6 5 External Reset IC 49 4 SYSTEM CLOCK 50 4 1 OVERVIEW 50 4 2 CLOCK BLOCK DIAGRAM 50 4 3 OSCM REGISTER 51 4 4 SYSTEM HIGH CLOCK 52 4 4 1 INTERNAL HIGH RC 52 4 4 2 EXTERNAL HI...

Page 5: ...EW 77 8 2 2 T0M MODE REGISTER 78 8 2 3 T0C COUNTING REGISTER 79 8 2 4 T0 TIMER OPERATION SEQUENCE 80 8 3 TIMER COUNTER 0 TC1 81 8 3 1 OVERVIEW 81 8 3 2 TC1M MODE REGISTER 82 8 3 3 TC1C COUNTING REGIST...

Page 6: ...BSOLUTE MAXIMUM RATING 104 12 2 ELECTRICAL CHARACTERISTIC 104 13 OTP PROGRAMMING PIN 105 13 1 1 The pin assignment of Easy Writer transition board socket 105 13 1 2 Programming Pin Mapping 106 14 MARK...

Page 7: ...electable Internal low clock RC type 16KHz 3V 32KHz 5V reference voltage 0 9V 1 0V 1 1V 1 2V and external reference input Four operating modes Normal mode Both high and low clock active Six interrupt...

Page 8: ...DIAGRAM INTERRUPT CONTROL EXTERNAL HIGH OSC ACC INTERNAL LOW RC TIMING GENERATOR RAM SYSTEM REGISTERS LVD Low Voltage Detector WATCHDOG TIMER TIMER COUNTER P0 P5 P1 PWM 1 BUZZER 1 ALU PC FLAGS IR OTP...

Page 9: ...N P5 1 7 22 XIN P0 3 P5 2 8 21 XOUT P0 4 P5 3 BZ1 PWM1 9 20 P2 1 P0 2 RST VPP 10 19 P2 0 P1 0 11 18 P1 7 P1 1 12 17 P1 6 P1 2 13 16 P1 5 P1 3 14 15 P1 4 SN8P26L34K SN8P26L34S SN8P26L34X P0 1 INT1 1 U...

Page 10: ...n Drain function controlled by P1OC register Built wakeup function P1 1 I O P1 1 Port 1 1 bi direction pin Schmitt trigger structure and built in pull up resisters as input mode Open Drain function co...

Page 11: ...he CM1O output Vss P5 2 0 I O P5 Port 5 bi direction pin Schmitt trigger structure and built in pull up resisters as input mode P5 3 BZ1 PWM1 I O P5 3 Port 5 3 bi direction pin Schmitt trigger structu...

Page 12: ...n Output Latch PnM PnUR Input Bus PnM Output Bus Port 1 0 P1 1 structure Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus P1OC Open Drain Port 0 3 0 4 structure Oscillator Code Option Int Os...

Page 13: ...SN8P26L00 Series 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 13 Preliminary Version 0 2 Port 0 2 structure Pin Ext Reset Code Option Int Bus Int Rst...

Page 14: ...NIT CPU 2 1 MEMORY MAP 2 1 1 PROGRAM MEMORY ROM 8K words ROM ROM 0000H Reset vector User reset vector Jump to user start address 0001H 0007H General purpose area 0008H Interrupt vector User interrupt...

Page 15: ...reset external reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset status...

Page 16: ...The following example shows the way to define the interrupt vector in the program memory Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is a unique buffer and only...

Page 17: ...user program User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from buffers RETI End o...

Page 18: ...LE1 L To set lookup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z overflow FFH 00 Y Y 1 NOP MOVC To...

Page 19: ...define a word 16 bits data DW 5105H DW 2012H The other example of look up table is to add Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register by B0...

Page 20: ...after PCL ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value and not change Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary B0ADD PCL A PCL P...

Page 21: ...routine begin from next RAM boundary 0x0100 Example JMP_A operation Before compiling program ROM address B0MOV A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X00FD JM...

Page 22: ...address to end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end of co...

Page 23: ...r external high clock oscillator High_Clk 4M X tal Standard crystal resonator e g 4M for external high clock oscillator Always_On Watchdog timer is always on enable even in power down and green mode E...

Page 24: ...4 Preliminary Version 0 2 2 1 3 DATA MEMORY RAM 240 X 8 bit RAM Address RAM location 000h Bank 0 02Fh General purpose area 080h 80h FFh of Bank 0 store system registers 128 bytes System register BANK...

Page 25: ...d ROM addressing register P1W Port 1 wakeup register RBANK Ram bank selection register CMPnM Comparator control register HL RAM HL indirect addressing index pointer PEDGE P0 0 edge direction register...

Page 26: ...0D9H T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 R W T0C 0DAH IREN CREN R W TC0M 0DBH TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 R W TC0C 0DCH TC1ENB TC1rate2 TC1rate1 TC1rate0 TC1CKS ALOAD1 TC1OUT...

Page 27: ...all the 0 and 1 as it indicates in the above table 2 All of register names had been declared in SN8ASM assembler 3 One bit name had been declared in SN8ASM assembler with F prefix code 4 b0bset b0bclr...

Page 28: ...be access by B0MOV instruction during the instant addressing mode Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Write...

Page 29: ...1 1 Reset by external Reset Pin Bit 5 LVD30 LVD 3 0V operating flag and only support LVD code option is LVD_H 0 Inactive VDD 3 0V 1 Active VDD 3 0V Bit 4 LVD24 LVD 2 4V operating flag and only support...

Page 30: ...10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are n...

Page 31: ...BUF0 JMP C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results unde...

Page 32: ...e by the three instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automatica...

Page 33: ...it 2 Bit 1 Bit 0 L LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 Read Write R W R W R W R W R W R W R W R W After reset X X X X X X X X Example If want to read a data from RAM address 20H of bank_0...

Page 34: ...W R W R W After reset 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 Read Write R W R W R W R W R W R W R W R W After reset Example Uses Y Z reg...

Page 35: ...tore high byte data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6 Bit...

Page 36: ...working register 2 2 2 DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC Example Move 0x12 RAM location data into ACC B0MOV A 12H To get a conten...

Page 37: ...struction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program counte...

Page 38: ...rvice routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7 Bit 6 Bit 5 Bit 4 B...

Page 39: ...TK1L 3 1 0 0 STK2H STK2L 4 0 1 1 STK3H STK3L 5 0 1 0 STK4H STK4L 6 0 0 1 STK5H STK5L 7 0 0 0 STK6H STK6L 8 1 1 1 STK7H STK7L 8 1 1 0 Stack Over error There are Stack Restore operations correspond to e...

Page 40: ...dition Description 0 0 Watchdog reset Watchdog timer overflow 0 1 Reserved 1 0 Power on reset and LVD reset Power voltage is lower than LVD detecting level 1 1 External reset External reset pin detect...

Page 41: ...dog timer by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is reset A...

Page 42: ...d V1 doesn t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some cond...

Page 43: ...minimum operating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating voltage above the system reset volt...

Page 44: ...k error the LVD can t be the protection and need to other reset methods More detail LVD information is in the electrical characteristic section The LVD is three levels design 1 8V 2 4V 3 0V and contro...

Page 45: ...m The watchdog is continuously counting until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and the system return to normal mode after reset sequence This meth...

Page 46: ...el the system keeps reset status and waits external reset pin released z System initialization All system registers is set as initial conditions and system is ready z Oscillator warm up Oscillator ope...

Page 47: ...ircuit and Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrica...

Page 48: ...ght R1 R2 value to conform the application In the circuit diagram condition the MCU s reset pin level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and the vo...

Page 49: ...VDD VSS VCC GND RST Reset IC VDD VSS RST Bypass Capacitor 0 1uF The external reset circuit also use external reset IC to enhance MCU reset performance This is a high cost and good effect solution By...

Page 50: ...r circuit ILRC 16KHz 3V Both the high speed clock and the low speed clock can be system clock Fosc The system clock in slow mode is divided by 4 to be the instruction cycle Fcpu Normal Mode High Clock...

Page 51: ...llator free run stop Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clock is high clock 1 Slow mode System clock is inte...

Page 52: ...rolled by IHRC_8M or IHRC_RTC code options In IHRC_8M mode the system clock is from internal 8MHz RC type oscillator and XIN XOUT pins are general purpose I O pins In IHRC_RTC mode the system clock is...

Page 53: ...mal speed ex 4MHz 32K option is for low speed ex 32768Hz MCU VCC GND C 20pF XIN XOUT VDD VSS C 20pF CRYSTAL Note Connect the Crystal Ceramic and C as near as possible to the XIN XOUT VSS pins of micro...

Page 54: ...cting external clock signal input to be system clock is by RC option of High_Clk code option The external clock signal is input from XIN pin XOUT pin is general purpose I O pin MCU VCC GND VSS VDD XIN...

Page 55: ...00 30 00 35 00 40 00 45 00 2 1 2 5 3 3 1 3 3 3 5 4 4 5 5 5 5 6 6 5 7 VDD V Freq KHz ILRC The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD Flosc Internal low...

Page 56: ...ruction cycle Fcpu This way is useful in RC mode Example Fcpu instruction cycle of external oscillator B0BSET P0M 0 Set P0 0 to be output mode for outputting Fcpu toggle signal B0BSET P0 0 Output Fcpu...

Page 57: ...iption MODE NORMAL SLOW GREEN POWER DOWN SLEEP REMARK EHOSC Running By STPHX By STPHX Stop IHRC Running By STPHX By STPHX Stop ILRC Running Running Running Stop EHOSC with RTC Running By STPHX Running...

Page 58: ...d oscillator is still running B0BCLR FCLKMD To set CLKMD 0 Example Switch slow mode to normal mode The external high speed oscillator stops If external high clock stop and program want to switch back...

Page 59: ...H To set T0 interval 10 ms B0BCLR FT0IEN To disable T0 interrupt service B0BCLR FT0IRQ To clear T0 interrupt request B0BSET FT0ENB To enable T0 timer Go into green mode B0BCLR FCPUM0 To set CPUMx 10 B...

Page 60: ...nto the normal mode Note Wakeup from green mode is no wakeup time because the clock doesn t stop in green mode The value of the wakeup time is as the following The Wakeup time 1 Fosc 2048 sec high clo...

Page 61: ...interrupt service is executed the GIE bit in STKP register will clear to 0 for stopping other interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept the ne...

Page 62: ...service routine when the returning interrupt service routine instruction RETI is executed 0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN TC1IEN T0IEN P01IEN P00IEN Read Write R W R W R W...

Page 63: ...st 1 INT0 interrupt request Bit 1 P01IRQ External P0 1 interrupt INT1 request flag 0 None INT1 interrupt request 1 INT1 interrupt request Bit 4 T0IRQ T0 timer interrupt request flag 0 None T0 interrup...

Page 64: ...nstruction save and load ACC PFLAG data into buffers and avoid main routine error after interrupt service routine finishing Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP...

Page 65: ...ble edge trigger function Port 0 Low level wakeup trigger and falling edge interrupt trigger Port 1 Low level wakeup trigger 1 Enable edge trigger function P0 0 Both Wakeup and interrupt trigger are c...

Page 66: ...ven when the P01IRQ is set to be 1 Users need to be cautious with the operation under multi interrupt situation Note The interrupt trigger direction of P0 1 is falling edge Example INT1 interrupt requ...

Page 67: ...st setup B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 74H Set T0C initial value 74H B0MOV T0C A Set T0 interval 10 ms B0BS...

Page 68: ...o be the 16us delay time 2 In RTC mode don t reset T0C in interrupt service routine Example T0 interrupt service routine with RTC function ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routi...

Page 69: ...ion Example TC1 interrupt request setup B0BCLR FTC1IEN Disable TC1 interrupt service B0BCLR FTC1ENB Disable TC1 timer MOV A 20H B0MOV TC1M A Set TC1 clock Fcpu 64 MOV A 74H Set TC1C initial value 74H...

Page 70: ...wo is using IEN and IRQ flags to decide which interrupt to be executed Users have to check interrupt control bit and interrupt request flag in interrupt routine Example Check the interrupt request und...

Page 71: ...t 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2M P27M P26M P25M P24M P23M P22M P21M P20M Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit...

Page 72: ...R P10R Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 0E2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2UR P27R P26R P25R P24R P23R P22R P21R P20R Read Write W W W W W W W W After reset 0...

Page 73: ...Bit 3 Bit 2 Bit 1 Bit 0 P1OC P11OC P10OC Read Write W W After reset 0 0 Bit 1 P11OC P1 1 open drain control bit 0 Disable open drain mode 1 Enable open drain mode Bit 0 P10OC P1 0 open drain control...

Page 74: ...26 P25 P24 P23 P22 P21 P20 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5 P54 P53 P52 P51 P50 Read Write R W R W R W R W...

Page 75: ...Speed oscillator sec VDD Internal Low RC Freq Watchdog Overflow Time 3V 16KHz 512ms 5V 32KHz 256ms Note If watchdog is Always_On mode it keeps running event under power down mode or green mode Watchd...

Page 76: ...watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An operation of watchdog timer is as following To clear the wat...

Page 77: ...ck frequency RTC timer Generates interrupts at real time intervals based on the selected clock source RTC function is only available in High_Clk code option IHRC_RTC Green mode wakeup function T0 can...

Page 78: ...e0 T0TB Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 0 T0TB RTC clock source control bit 0 Disable RTC T0 clock source from Fcpu 1 Enable RTC Bit 6 4 T0RATE 2 0 T0 internal clock select bi...

Page 79: ...pu 64 T0C initial value 256 T0 interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H The basic timer table interval time of T0 High speed mode Fcpu 4MHz 4 Low speed mode F...

Page 80: ...function is disabled B0BCLR FT0IRQ T0 interrupt request flag is cleared Set T0 timer rate MOV A 0xxx0000b The T0 rate control bits exist in bit4 bit6 of T0M The value is from x000xxxxb x111xxxxb B0MOV...

Page 81: ...to request interrupt service TC1 overflow time is 0xFF to 0X00 normally Under PWM mode TC1 overflow is decided by PWM cycle controlled by ALOAD1 and TC1OUT bits The main purposes of the TC1 timer is...

Page 82: ...tput control bit Only valid when PWM1OUT 0 0 Disable P5 3 is I O function 1 Enable P5 3 is output TC1OUT signal Bit 2 ALOAD1 Auto reload control bit Only valid when PWM1OUT 0 0 Disable TC1 auto reload...

Page 83: ...low per 256 count 1 0 1 64 0x00 0x3F xx000000b xx111111b Overflow per 64 count 1 1 0 32 0x00 0x1F xxx00000b xxx11111b Overflow per 32 count 0 1 1 1 16 0x00 0x0F xxxx0000b xxxx1111b Overflow per 16 cou...

Page 84: ...C1R1 TC1R0 Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of TC1R initial value is as following TC1R initial value N TC1 interrupt interval time input clock N is TC1 overflow boun...

Page 85: ...quency waveform is as following 1 2 3 4 1 2 3 4 TC0 Overflow Clock TC0OUT Buzzer Output Clock Example Setup TC1OUT output from TC1 to TC1OUT P5 3 The external high speed clock is 4MHz The TC1OUT frequ...

Page 86: ...ce or B0BSET FTC1CKS Select TC1 external clock source Set TC1 timer auto load mode B0BCLR FALOAD1 Enable TC1 auto reload function or B0BSET FALOAD1 Disable TC1 auto reload function Set TC1 interrupt i...

Page 87: ...es low When the counter reaches zero the PWM output is forced high The low to high ratio duty of the PWM1 output is TC1R 256 64 32 16 ALOAD1 TC1OUT PWM duty range TC1C valid value TC1R valid bits valu...

Page 88: ...RQ AND PWM DUTY In PWM mode the frequency of TC1IRQ is depended on PWM duty range From following diagram the TC1IRQ frequency is related with PWM duty TC1C Value PWM1 Output Duty Range 0 255 PWM1 Outp...

Page 89: ...00000B B0MOV TC1M A Set the TC1 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 B0MOV TC1C A B0MOV TC1R A B0BCLR FTC1OUT Set duty range as 0 256 255 256 B0BCLR FALOAD1 B0BSET FPWM1OUT Enable PWM1 o...

Page 90: ...e PWM will output logic Low If TC1C is changed in certain period the PWM duty will change immediately If TC1R is fixed all the time the PWM waveform is also the same TC1C overflow and TC1IRQ set TC1C...

Page 91: ...cycle PWM outputs correct duty In period 4 the new TC1R value is smaller than the old TC1R value If setting new TC1R is before PWM output low system is getting TC1C TC1R result and making PWM output l...

Page 92: ...rce is only from Fhosc external high clock source eg 4MHz crystal If external oscillator is 4MHz the TC0 clock rate is 4MHz TC0 only generate IR output and no interrupt function When enable IR output...

Page 93: ...carry signal output control bit 0 Disable IROUT pin is output low status 1 Enable IROUT pin outputs IR carry signal Note IR carry output condition is IREN 1 and CREN 1 If CREN 1 and IREN 0 the IROUT...

Page 94: ...is stored in 1 st buffer Until TC0 overflow occurs the new value moves to real TC0R buffer 0CDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC0R TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 Rea...

Page 95: ...D4 TC0D3 TC0D2 TC0D1 TC0D0 Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of TC0Dinitial value is as following TC0D initial value TC0R 256 TC0R 1 IR duty Example Set TC0D for 38KH...

Page 96: ...R OUTPUT OPERATION SEQUENCE Set TC0C and TC0R for IR cycle MOV A IRCYCVAL TC0C TC0R value for IR cycle MOV TC0C A MOV TC0R A Set TC0D for IR duty MOV A IRDUTYVAL TC0D value for IR duty MOV TC0D A Enab...

Page 97: ...1V 1 0V 0 9V CM1OEN CM1EN CM1EN CM1REF CM1N CN1O CM1P Comparator 0 Comparator 1 Comparator Reference Voltage CM0OUT Flag CM1IRQ CM1IEN Comparator 1 Interrupt CM1OUT Flag Comparator 0 Pin assignment CM...

Page 98: ...Internal Logic Internal Reference Voltage CMnN CNnO GPIO CMnP Comparator Comparator Internal Logic CMnN CNnO GPIO CMnP GPIO Comparator Comparator Internal Logic Internal Reference Voltage CMnEN 1 CMnO...

Page 99: ...pt request flag 0 CM0P voltage or comparator 0 reference voltage is less than CM0N voltage 1 CM0P voltage or comparator 0 reference voltage is larger than CM0N voltage Bit 4 CM0OEN Comparator 0 output...

Page 100: ...ence voltage is less than CM1N voltage 1 CM1P voltage or comparator 1 reference voltage is larger than CM1N voltage Bit 4 CM1OEN Comparator 1 output pin control bit 0 Disable CM1O pin is GPIO 1 Enable...

Page 101: ...heck battery 2 0V Example Use 2 ch comparators to detect battery status The battery voltage less than 2 2V is low battery status The battery voltage less than 2 0V is no battery status This case is po...

Page 102: ...8P26L00 Series 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 102 Preliminary Version 0 2 JMP NoBat Is no battery status go to no battery routine Low battery process LowBat No battery process NoB...

Page 103: ...M A A xor M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 N R RRC M A RRC M 1 O RRCM M M RRC M 1 N C RLC M A RLC M 1 E RLCM...

Page 104: ...dd 25 C 2 uA I O port pull up resistor Rup Vin Vss Vdd 3V 100 200 300 K I O port input leakage current Ilekg Pull up resistor disable Vin Vdd 2 uA I O output source current IoH Vop Vdd 0 5V 9 sink cur...

Page 105: ...TPCLK DIP3 3 46 DIP46 D0 8 7 D1 DIP4 4 45 DIP45 D2 10 9 D3 DIP5 5 44 DIP44 D4 12 11 D5 DIP6 6 43 DIP43 D6 14 13 D7 DIP7 7 42 DIP42 VPP 16 15 VDD DIP8 8 41 DIP41 RST 18 17 HLS DIP9 9 40 DIP40 ALSB PDB...

Page 106: ...6L34KSX SN8P26L32PS SN8P26L321P S X EZ Writer Connector OTP IC JP3 Pin Assigment Number Name Number Pin Number Pin Number Pin 1 VDD 2 VDD 2 VDD 3 VDD 2 GND 4 VSS 4 VSS 5 VSS 3 CLK 6 P5 0 5 P5 0 6 P5 0...

Page 107: ...CU for order or obtain information This definition is only for Blank OTP MCU 14 2 MARKING INDETIFICATION SYSTEM Title SONiX 8 bit MCU Production ROM Type P OTP A MASK Material B PB Free Package G Gree...

Page 108: ...ree Package SN8P26L32PG OTP 26L32 P DIP 0 70 Green Package SN8P26L32SG OTP 26L32 SOP 0 70 Green Package SN8P26L321PG OTP 26L321 P DIP 0 70 Green Package SN8P26L321SG OTP 26L321 SOP 0 70 Green Package...

Page 109: ...TION 15 1 SK DIP 28 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 114 0 130 0 135 2 896 3 302 3 429 D 1 390 1 390 1 400 35 306 35 306 35 560 E 0 310 7 874 E1 0 283 0 28...

Page 110: ...2 SOP 28 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 697 0 705 0 713 17 704 17 907 18 110 E 0 291 0 295 0 299 7 391 7 4...

Page 111: ...R MAX MIN NOR MAX SYMBOLS inch mm A 0 08 2 13 A1 0 00 0 01 0 05 0 25 A2 0 06 0 07 0 07 1 63 1 75 1 88 b 0 01 0 01 0 22 0 38 C 0 00 0 01 0 09 0 20 D 0 39 0 40 0 41 9 90 10 20 10 50 E 0 29 0 31 0 32 7 4...

Page 112: ...DIP 18 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 0 880 0 900 0 920 22 352 22 860 23 368 E 0 300 7 620 E1 0 245 0 250 0 255 6 22...

Page 113: ...5 SOP 18 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 447 0 455 0 463 11 354 11 557 11 760 E 0 291 0 295 0 299 7 391 7 4...

Page 114: ...DIP 20 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 0 980 1 030 1 060 24 892 26 162 26 924 E 0 300 7 620 E1 0 245 0 250 0 255 6 22...

Page 115: ...7 SOP 20 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 496 0 502 0 508 12 598 12 751 12 903 E 0 291 0 295 0 299 7 391 7 4...

Page 116: ...0 006 0 010 0 100 0 150 0 250 A2 0 059 1 500 b 0 008 0 010 0 012 0 200 0 254 0 300 c 0 007 0 008 0 010 0 180 0 203 0 250 D 0 337 0 341 0 344 8 560 8 660 8 740 E 0 228 0 236 0 244 5 800 6 000 6 200 E1...

Page 117: ...Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors...

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