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SN8P2624

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 84

Version 0.3

8.4.3 PWM Duty with TCxR Changing

In PWM mode, the system will compare TC1C and TC1R all the time. When TC1C<TC1R, the PWM will output logic
“High”, when TC1C

≧

TC1R, the PWM will output logic “Low”. If TC1C is changed in certain period, the PWM duty will

change in next PWM period. If TC1R is fixed all the time, the PWM waveform is also the same.

TC1C overflow
and TC1IRQ set

TC1C = TC1R

0xFF

TC1C Value

0x00

PWM1 Output

1

2

3

4

5

6

7

Period

Above diagram is shown the waveform with fixed TC1R. In every TC1C overflow PWM output “High, when TC1C

≧

TC1R PWM output ”Low”. If TC1R is changing in the program processing, the PWM waveform will became as following
diagram.

1

1st PWM

2

Update PWM Duty

3

2nd PWM

4

Update PWM Duty

0xFF

TC1C Value

0x00

PWM1 Output

Period

5

3th PWM

TC1C overflow
and TC1IRQ set

Old TC1R

Old TC1R

New TC1R

New TC1R

Update New TC1R!
Old TC1R < TC1C < New TC1R

Update New TC1R!
New TC1R < TC1C < Old TC1R

TC1C > = TC1R
PWM High > Low

TC1C < TC1R
PWM Low > High

In period 2 and period 4, new Duty (TC1R) is set. TC1 is double buffer design. The PWM still keeps the same duty in
period 2 and period 4, and the new duty is changed in next period. By the way, system can avoid the PWM not
changing or H/L changing twice in the same cycle and will prevent the unexpected or error operation.

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Summary of Contents for SN8P2624

Page 1: ...authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of t...

Page 2: ...8P26242 part number VER 0 2 Nov 2005 1 ADD Brown Out reset circuit 2 Working Voltage vs Frequency graphs VER 0 3 Nov 2005 1 Modify Topr value Dec 2005 2 Modify Brown Out Reset description 3 Remove pow...

Page 3: ...2 1 1 4 JUMP TABLE DESCRIPTION 18 2 1 1 5 CHECKSUM CALCULATION 20 2 1 2 CODE OPTION TABLE 21 2 1 3 DATA MEMORY RAM 22 2 1 4 SYSTEM REGISTER 23 2 1 4 1 SYSTEM REGISTER TABLE 23 2 1 4 2 SYSTEM REGISTER...

Page 4: ...et Circuit 43 3 6 4 Voltage Bias Reset Circuit 44 3 6 5 External Reset IC 45 4 4 4 SYSTEM CLOCK 46 4 1 OVERVIEW 46 4 2 CLOCK BLOCK DIAGRAM 46 4 3 OSCM REGISTER 47 4 4 SYSTEM HIGH CLOCK 48 4 4 1 EXTERN...

Page 5: ...2 TIMER 0 T0 73 8 2 1 OVERVIEW 73 8 2 2 T0M MODE REGISTER 73 8 2 3 T0C COUNTING REGISTER 74 8 2 4 T0 TIMER OPERATION SEQUENCE 75 8 3 TIMER COUNTER 0 TC1 76 8 3 1 OVERVIEW 76 8 3 2 TC1M MODE REGISTER 7...

Page 6: ...ion 0 3 11 1 1 EASY WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT 89 11 1 2 WRITER V2 5 AND V3 0 TRANSITION BOARD SOCKET PIN ASSIGNMENT 89 11 1 3 PROGRAMMING PIN MAPPING 90 1 1 12 2 2 PACKAGE INFORMAT...

Page 7: ...Bi directional P0 P1 P2 P5 Input only pin P0 2 Dual system clocks Programmable open drain P1 0 P1 1 External high clock RC type up to 10 MHz Wakeup P0 P1 level change trigger External high clock Crys...

Page 8: ...Page 8 Version 0 3 1 2 SYSTEM BLOCK DIAGRAM INTERRUPT CONTROL EXTERNAL HIGH OSC ACC INTERNAL LOW RC TIMING GENERATOR RAM SYSTEM REGISTERS LVD Low Voltage Detector WATCHDOG TIMER TIMER COUNTER P0 P5 P1...

Page 9: ...N8P2624S SOP 28 pins SN8P2624X SSOP 28 pins P0 1 INT1 1 U 28 RST VPP P0 2 VDD 2 27 XIN P5 4 3 26 XOUT Fcpu VSS 4 25 P2 7 P0 0 INT0 5 24 P2 6 P5 0 6 23 P2 5 P5 1 7 22 P2 4 P5 2 8 21 P2 3 P5 3 BZ1 PWM1...

Page 10: ...ut mode Built in pull up resisters Built in wakeup function INT0 trigger pin Schmitt trigger P0 1 INT1 I O Port 0 1 bi direction pin Schmitt trigger structure as input mode Built in pull up resisters...

Page 11: ...0 3 1 5 PIN CIRCUIT DIAGRAMS Port 0 1 2 5 structure Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus Port 1 0 P1 1 structure Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus P1OC...

Page 12: ...2 1 MEMORY MAP 2 1 1 PROGRAM MEMORY ROM 2K words ROM ROM 0000H Reset vector User reset vector 0001H Jump to user start address 0007H General purpose area 0008H Interrupt vector User interrupt vector 0...

Page 13: ...ernal reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset status from NT0 N...

Page 14: ...wing example shows the way to define the interrupt vector in the program memory Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is a unique buffer and only one level...

Page 15: ...am User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from buffers RETI End of interrup...

Page 16: ...et lookup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z overflow FFH 00 Y Y 1 NOP MOVC To lookup dat...

Page 17: ...ord 16 bits data DW 5105H DW 2012H The other example of loop up table is to add Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register by B0ADD ADD in...

Page 18: ...ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value and not change Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary B0ADD PCL A PCL PCL ACC PCH...

Page 19: ...gin from next RAM boundary 0x0100 Example JMP_A operation Before compiling program ROM address B0MOV A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X00FD JMP A0POINT...

Page 20: ...end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end of code AAA INC...

Page 21: ...must be disabled Fhosc 2 Instruction cycle is 2 oscillator clocks Notice In Fosc 2 Noise Filter must be disabled Fhosc 4 Instruction cycle is 4 oscillator clocks Fcpu Fhosc 8 Instruction cycle is 8 os...

Page 22: ...iX TECHNOLOGY CO LTD Page 22 Version 0 3 2 1 3 DATA MEMORY RAM 64 X 8 bit RAM Address RAM location 000h 03Fh General purpose area 080h 080h 0FFh of Bank 0 store system registers 128 bytes System regis...

Page 23: ...buffer H L Working HL and ROM addressing register Y Z Working YZ and ROM addressing register P1W Port 1 wakeup register PEDGE P0 0 edge direction register PnM Port n input output mode register Pn Port...

Page 24: ...DH TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0 R W TC1C 0DEH TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0 W TC1R 0DFH GIE STKPB2 STKPB1 STKPB0 R W STKP 0E0H P01R P00R W P0UR 0E1H P17R P16R P15R...

Page 25: ...by B0MOV instruction during the instant addressing mode Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Write ACC data...

Page 26: ...Reset Status 0 0 Watch dog time out 0 1 Reserved 1 0 Reset by LVD 1 1 Reset by external Reset Pin Bit 2 C Carry flag 1 Addition with carry subtraction without borrowing rotation with shifting out logi...

Page 27: ...Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are nine instructions...

Page 28: ...C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results underflow of 0...

Page 29: ...hree instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automatically If PCL...

Page 30: ...Bit 0 L LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 Read Write R W R W R W R W R W R W R W R W After reset X X X X X X X X Example If want to read a data from RAM address 20H of bank_0 it can use...

Page 31: ...After reset 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 Read Write R W R W R W R W R W R W R W R W After reset Example Uses Y Z register as...

Page 32: ...byte data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6 Bit 5 Bit 4...

Page 33: ...ample Move 0x12 RAM location data into ACC B0MOV A 12H To get a content of RAM location 0x12 of bank 0 and save in ACC Example Move ACC data into 0x12 RAM location B0MOV 12H A To get a content of ACC...

Page 34: ...are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program counter PC data...

Page 35: ...service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7 Bit 6 Bit 5 Bit...

Page 36: ...0 STK2H STK2L 4 0 1 1 STK3H STK3L 5 0 1 0 STK4H STK4L 6 0 0 1 STK5H STK5L 7 0 0 0 STK6H STK6L 8 1 1 1 STK7H STK7L 8 1 1 0 Stack Over error There are Stack Restore operations correspond to each push o...

Page 37: ...0 0 Watchdog reset Watchdog timer overflow 0 1 Reserved 1 0 Power on reset and LVD reset Power voltage is lower than LVD detecting level 1 1 External reset External reset pin detect low level status...

Page 38: ...by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is reset After watch...

Page 39: ...t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some conditions DC...

Page 40: ...perating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating voltage above the system reset voltage 3 4 3...

Page 41: ...d the execution error the watchdog timer can t be clear by program The watchdog is continuously counting until overflow occurrence The overflow signal of watchdog timer triggers the system to reset an...

Page 42: ...tem keeps reset status and waits external reset pin released z System initialization All system registers is set as initial conditions and system is ready z Oscillator warm up Oscillator operation is...

Page 43: ...Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrical Over str...

Page 44: ...value to conform the application In the circuit diagram condition the MCU s reset pin level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and the voltage lowe...

Page 45: ...CC GND RST Reset IC VDD VSS RST Bypass Capacitor 0 1uF The external reset circuit also use external reset IC to enhance MCU reset performance This is a high cost and good effect solution By different...

Page 46: ...cle Fcpu Normal Mode High Clock Fcpu Fhosc N N 1 8 Select N by Fcpu code option Slow Mode Low Clock Fcpu Flosc 4 SONIX provides a Noise Filter controlled by code option In high noisy situation the noi...

Page 47: ...e run stop Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clock is high clock 1 Slow mode System clock is internal low c...

Page 48: ...gh clock is external high speed oscillator The typical frequency is 12MHz 4M The high clock is external oscillator The typical frequency is 4MHz 4 4 1 EXTERNAL HIGH CLOCK External high clock includes...

Page 49: ...s for normal speed ex 4MHz MCU VCC GND C 20pF XIN XOUT VDD VSS C 20pF CRYSTAL Note Connect the Crystal Ceramic and C as near as possible to the XIN XOUT VSS pins of micro controller 4 4 1 2 RC Selecti...

Page 50: ...rnal clock signal input to be system clock is by RC option of High_Clk code option The external clock signal is input from XIN pin XOUT pin is general purpose I O pin MCU VCC GND VSS VDD XIN XOUT Exte...

Page 51: ...00 35 00 40 00 45 00 2 1 2 5 3 3 1 3 3 3 5 4 4 5 5 5 5 6 6 5 7 VDD V Freq KHz ILRC The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD Flosc Internal low RC osc...

Page 52: ...cle Fcpu This way is useful in RC mode Example Fcpu instruction cycle of external oscillator B0BSET P0M 0 Set P0 0 to be output mode for outputting Fcpu toggle signal B0BSET P0 0 Output Fcpu toggle si...

Page 53: ...ive T0 Timer Time Out External Reset Circuit Active System Mode Switching Diagram Operating mode description MODE NORMAL SLOW GREEN POWER DOWN SLEEP REMARK EHOSC Running By STPHX By STPHX Stop ILRC Ru...

Page 54: ...or is still running B0BCLR FCLKMD To set CLKMD 0 Example Switch slow mode to normal mode The external high speed oscillator stops If external high clock stop and program want to switch back normal mod...

Page 55: ...A To set T0 clock Fcpu 64 MOV A 74H B0MOV T0C A To set T0C initial value 74H To set T0 interval 10 ms B0BCLR FT0IEN To disable T0 interrupt service B0BCLR FT0IRQ To clear T0 interrupt request B0BSET F...

Page 56: ...TIME When the system is in power down mode sleep mode the high clock oscillator stops When waked up from power down mode MCU waits for 2048 external high speed oscillator clocks as the wakeup time to...

Page 57: ...tem up to normal mode The Port 0 and Port 1 have wakeup function Port 0 wakeup function always enables but the Port 1 is controlled by the P1W register 0C0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B...

Page 58: ...pt service is executed the GIE bit in STKP register will clear to 0 for stopping other interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept the next inter...

Page 59: ...outine when the returning interrupt service routine instruction RETI is executed 0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN TC1IEN T0IEN P01IEN P00IEN Read Write R W R W R W R W After...

Page 60: ...interrupt request Bit 1 P01IRQ External P0 1 interrupt INT1 request flag 0 None INT1 interrupt request 1 INT1 interrupt request Bit 4 T0IRQ T0 timer interrupt request flag 0 None T0 interrupt request...

Page 61: ...save and load ACC PFLAG data into buffers and avoid main routine error after interrupt service routine finishing Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is...

Page 62: ...Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDGE P00G1 P00G0 Read Write R W R W After reset 1 0 Bit 4 3 P00G 1 0 P0 0 interrupt trigger edge control bits 00 reserved 01 rising edge 10 falling edge 11 r...

Page 63: ...he P01IRQ is set to be 1 Users need to be cautious with the operation under multi interrupt situation Note The interrupt trigger direction of P0 1 is falling edge Example INT1 interrupt request setup...

Page 64: ...t setup B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 74H Set T0C initial value 74H B0MOV T0C A Set T0 interval 10 ms B0BSE...

Page 65: ...e TC1 interrupt request setup B0BCLR FTC1IEN Disable TC1 interrupt service B0BCLR FTC1ENB Disable TC1 timer MOV A 20H B0MOV TC1M A Set TC1 clock Fcpu 64 MOV A 74H Set TC1C initial value 74H B0MOV TC1C...

Page 66: ...g IEN and IRQ flags to decide which interrupt to be executed Users have to check interrupt control bit and interrupt request flag in interrupt routine Example Check the interrupt request under multi i...

Page 67: ...it 1 Bit 0 P2M P27M P26M P25M P24M P23M P22M P22M P20M Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5M P54M P53M P52M P5...

Page 68: ...W W W After reset 0 0 0 0 0 0 0 0 0E2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2UR P27R P26R P25R P24R P23R P22R P21R P20R Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 0E5H Bit 7 B...

Page 69: ...2 Bit 1 Bit 0 P1OC P11OC P10OC Read Write W W After reset 0 0 Bit 0 P10OC P10 open drain control bit 0 Disable open drain mode 1 Enable open drain mode Bit 1 P11OC P11 open drain control bit 0 Disable...

Page 70: ...R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5 P54 P53 P52 P51 P50 Read Write R W R W R W R W R W After reset 0 0 0 0 0 Note The P02 ke...

Page 71: ...scillator sec VDD Internal Low RC Freq Watchdog Overflow Time 3V 16KHz 512ms 5V 32KHz 256ms Note If watchdog is Always_On mode it keeps running event under power down mode or green mode Watchdog clear...

Page 72: ...timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An operation of watchdog timer is as following To clear the watchdog time...

Page 73: ...s at specific time intervals based on the selected clock frequency Green mode wakeup function T0 can be green mode wake up time as T0ENB 1 System will be wake up by T0 time out Fcpu T0 Rate Fcpu 2 Fcp...

Page 74: ...ternal 4MHz Fcpu Fosc 4 Select T0RATE 010 Fcpu 64 T0C initial value 256 T0 interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H The basic timer table interval time of T0...

Page 75: ...B0BCLR FT0ENB T0 timer B0BCLR FT0IEN T0 interrupt function is disabled B0BCLR FT0IRQ T0 interrupt request flag is cleared Set T0 timer rate MOV A 0xxx0000b The T0 rate control bits exist in bit4 bit6...

Page 76: ...t interrupt service TC1 overflow time is 0xFF to 0X00 normally Under PWM mode TC1 overflow is decided by PWM cycle controlled by ALOAD1 and TC1OUT bits The main purposes of the TC1 timer is as followi...

Page 77: ...ol bit Only valid when PWM1OUT 0 0 Disable P5 3 is I O function 1 Enable P5 3 is output TC1OUT signal Bit 2 ALOAD1 Auto reload control bit Only valid when PWM1OUT 0 0 Disable TC1 auto reload function...

Page 78: ...6 count 1 0 1 64 0x00 0x3F xx000000b xx111111b Overflow per 64 count 1 1 0 32 0x00 0x1F xxx00000b xxx11111b Overflow per 32 count 0 1 1 1 16 0x00 0x0F xxxx0000b xxxx1111b Overflow per 16 count 1 256 0...

Page 79: ...Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of TC1R initial value is as following TC1R initial value N TC1 interrupt interval time input clock N is TC1 overflow boundary number...

Page 80: ...eform is as following 1 2 3 4 1 2 3 4 TC0 Overflow Clock TC0OUT Buzzer Output Clock Example Setup TC1OUT output from TC1 to TC1OUT P5 3 The external high speed clock is 4MHz The TC1OUT frequency is 0...

Page 81: ...ET FTC1CKS Select TC1 external clock source Set TC1 timer auto load mode B0BCLR FALOAD1 Enable TC1 auto reload function or B0BSET FALOAD1 Disable TC1 auto reload function Set TC1 interrupt interval ti...

Page 82: ...ster with 00H Under PWM operating to change the PWM s duty cycle is to modify the TC1R Note TC1 is double buffer design Modifying TC1R to change PWM duty by program there is no glitch and error duty s...

Page 83: ...range From following diagram the TC1IRQ frequency is related with PWM duty TC1 Overflow TC1IRQ 1 PWM1 Output Duty Range 0 15 0xFF TC1C Value 0x00 PWM1 Output Duty Range 0 31 0xFF TC1C Value 0x00 PWM1...

Page 84: ...1C overflow PWM output High when TC1C TC1R PWM output Low If TC1R is changing in the program processing the PWM waveform will became as following diagram 1 1st PWM 2 Update PWM Duty 3 2nd PWM 4 Update...

Page 85: ...OV TC1M A Set the TC1 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 B0MOV TC1C A B0MOV TC1R A B0BCLR FTC1OUT Set duty range as 0 256 255 256 B0BCLR FALOAD1 B0BSET FPWM1OUT Enable PWM1 output to P...

Page 86: ...r M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 N R RRC M A RRC M 1 O RRCM M M RRC M 1 N C RLC M A RLC M 1 E RLCM M M RLC M...

Page 87: ...pin Vss 0 2Vdd V ViH1 All input ports 0 7Vdd Vdd V Input High Voltage ViH2 Reset pin 0 9Vdd Vdd V Reset pin leakage current Ilekg Vin Vdd 2 uA Vin Vss Vdd 3V 100 200 300 I O port pull up resistor Rup...

Page 88: ...DD 10 3 CHARACTERISTIC GRAPHS The Graphs in this section are for design guidance not tested or guaranteed In some graphs the data presented are outside specified operating range This is for informatio...

Page 89: ...38 JP2 for Writer V3 0 transition board DIP13 13 36 DIP36 DIP14 14 35 DIP35 DIP15 15 34 DIP34 DIP16 16 33 DIP33 DIP17 17 32 DIP32 DIP18 18 31 DIP31 DIP19 19 30 DIP30 DIP20 20 29 DIP29 DIP21 21 28 DIP2...

Page 90: ...ector EZ Writer Writer V3 0 Connector OTP IC JP3 Pin Assigment Number Name Number Name Number Pin Number Pin 2 VDD 1 VDD 2 VDD 1 GND 2 GND 4 VSS 4 CLK 3 CLK 6 P5 0 3 CE 4 CE 6 PGM 5 PGM 10 P1 0 5 OE 6...

Page 91: ...1 SK DIP 28 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 114 0 130 0 135 2 896 3 302 3 429 D 1 390 1 390 1 400 35 306 35 306 35 560 E 0 310 7 874 E1 0 283 0 288 0 293...

Page 92: ...IN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 697 0 705 0 713 17 704 17 907 18 110 E 0 291 0 295 0 299 7 391 7 493 7 595 H...

Page 93: ...OR MAX SYMBOLS inch mm A 0 08 2 13 A1 0 00 0 01 0 05 0 25 A2 0 06 0 07 0 07 1 63 1 75 1 88 b 0 01 0 01 0 22 0 38 C 0 00 0 01 0 09 0 20 D 0 39 0 40 0 41 9 90 10 20 10 50 E 0 29 0 31 0 32 7 40 7 80 8 20...

Page 94: ...ay occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and dis...

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