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SN8P2511

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 82

Version 1.2

1

1

1

0

0

0

ELECTRICAL CHARACTERISTIC

10.1 ABSOLUTE MAXIMUM RATING

Supply voltage (Vdd)…………………………………………………………………………………………………………………….……………… - 0.3V ~ 6.0V
Input in voltage (Vin)…………………………………………………………………………………………………………………….… Vss – 0.2V ~ Vdd + 0.2V
Operating ambient temperature (Topr)

SN8P2511P, SN8P2511S, SN8P2511X

……………………………………..……………………...………..………………………..........0



C ~ + 70



C

Storage ambient temperature (Tstor) ………………………………………………………………….………………………………………… –40



C ~ + 125



C

10.2 ELECTRICAL CHARACTERISTIC



DC CHARACTERISTIC

(All of voltages refer to Vss, Vdd = 5.0V, Fosc = 4MHz, Fcpu=1MHz, ambient temperature is 25



C unless otherwise note.)

PARAMETER

SYM.

DESCRIPTION

MIN.

TYP.

MAX.

UNIT

Operating voltage

Vdd

Normal mode, Vpp = Vdd,

-40



C ~85



C,

Fcpu = 1MHz

2.2

-

5.5

V

RAM Data Retention voltage

Vdr

1.5

-

-

V

*Vdd rise rate

Vpor

Vdd rise rate to ensure internal power-on reset

0.05

-

-

V/ms

Input Low Voltage

ViL1

All input ports

Vss

-

0.3Vdd

V

ViL2

Reset pin

Vss

-

0.2Vdd

V

Input High Voltage

ViH1

All input ports

0.7Vdd

-

Vdd

V

ViH2

Reset pin

0.8Vdd

-

Vdd

V

Reset pin leakage current

Ilekg

Vin = Vdd,

25



C

-

-

2

uA

I/O port input leakage current

Ilekg

Pull-up resistor disable, Vin = Vdd

-

-

2

uA

I/O port pull-up resistor

Rup

Vin = Vss , Vdd = 3V

100

200

300

K



Vin = Vss , Vdd = 5V

50

100

180

I/O output source current

IoH

Vop = Vdd

– 0.5V

8

15

-

mA

sink current

IoL

Vop = Vss + 0.5V

8

15

-

*INTn trigger pulse width

Tint0

INT0 interrupt request pulse width

2/fcpu

-

-

cycle

Supply Current

Idd1

Run Mode
(No loading,
Fcpu = Fosc/4)

Vdd= 5V, 4Mhz

-

3

5

mA

Vdd= 3V, 4Mhz

-

1.5

2

mA

Idd2

Slow Mode
(Internal low RC,
Stop high clock)

Vdd=5V, ILRC 32Khz

-

20

40

uA

Vdd=3V, ILRC 16Khz

-

5

10

uA

Idd3

Sleep Mode

Vdd= 5V,

25



C

-

0.8

1.6

uA

Vdd= 3V,

25



C

-

0.7

1.4

uA

Idd4

Green Mode
(No loading,
Fcpu = Fosc/4,
Watchdog Disable)

Vdd= 5V, 4Mhz

-

0.6

1.2

mA

Vdd= 3V, 4Mhz

-

0.25

0.5

mA

Vdd=5V, ILRC 32Khz

-

15

30

uA

Vdd=3V, ILRC 16Khz

-

3

6

uA

Internal High Oscillator Freq.

Fihrc

Internal Hihg RC
(IHRC)

25



C,

Vdd= 5V,Fcpu = 1MHz

15.68

16

16.32

Mhz

LVD Voltage

Vdet0 Low voltage reset level,

0



C ~ + 70



C

1.6

2.0

2.2

V

Vdet1

Low voltage reset/indicator level. Fcpu = 1 MHz,

0



C ~ + 70



C

1.8

2.4

3

V

Vdet2

Low voltage reset/indicator level. Fcpu = 1 MHz,

0



C ~ + 70



C

2.5

3.6

4.5

V

External oscillator (32KHz)

match capacitor

C

32K

Capacitor selection for

crystal oscillator in 32KHz

20

27

33

pF

“

*

” These parameters are for design reference, not tested.

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Summary of Contents for SN8P2511

Page 1: ...or us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX prod...

Page 2: ...ge 2 Version 1 2 AMENDENT HISTORY Version Date Description VER 1 0 Feb 2012 First issue VER 1 1 Apr 2012 Add features selection table and migration section VER 1 2 Jan 2013 Modify 32KHz oscillator to...

Page 3: ...EFINITION of SYSTEM REGISTER 20 2 2 2 ACCUMULATOR 21 2 2 3 PROGRAM FLAG 22 2 2 4 PROGRAM COUNTER 23 2 2 5 Y Z REGISTERS 25 2 2 6 R REGISTER 25 2 3 ADDRESSING MODE 26 2 3 1 IMMEDIATE ADDRESSING MODE 26...

Page 4: ...5 2 NORMAL MODE 47 5 3 SLOW MODE 47 5 4 POWER DOWN MODE 47 5 5 GREEN MODE 48 5 6 OPERATING MODE CONTROL MACRO 49 5 7 WAKEUP 50 5 7 1 OVERVIEW 50 5 7 2 WAKEUP TIME 50 5 7 3 P1W WAKEUP CONTROL REGISTER...

Page 5: ...81 1 1 10 0 0 ELECTRICAL CHARACTERISTIC 82 10 1 ABSOLUTE MAXIMUM RATING 82 10 2 ELECTRICAL CHARACTERISTIC 82 10 3 CHARACTERISTIC GRAPHS 83 1 1 11 1 1 DEVELOPMENT TOOL 84 11 1 SN8P2511 2501A B C EV KIT...

Page 6: ...bits One 8 bit basic timer with RTC 0 5Sec 4 levels stack buffer One 8 bit timer with external event counter Buzzer and PWM TC0 3 interrupt sources 2 internal interrupts T0 TC0 On chip watchdog timer...

Page 7: ...R COUNTER P0 P5 P1 PWM BUZZER ALU PC FLAGS IR OTP ROM PWM0 BUZZER0 P2 1 3 PIN ASSIGNMENT SN8P2511P P DIP 14 pins SN8P2511S SOP 14 pins P2 2 1 U 14 P2 3 P2 1 2 13 P2 4 P2 0 3 12 P2 5 VDD 4 11 VSS P1 3...

Page 8: ...put pin P1 0 I O P1 0 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up Programmable open drain structure P1 2 XOUT I O XOUT Oscillator output pi...

Page 9: ...Reset Oscillator shared pin structure Pull Up Resistor Output Latch Pin PnUR PnM I O Input Bus I O Output Bus PnM High_Clk Code Option Oscillator Driver GPIO structure Pull Up Resistor Output Latch Pi...

Page 10: ...pt vector User interrupt vector 0009H General purpose area User program 000FH 0010H 0011H 03FCH End of user program 03FDH Reserved 03FEH 03FFH The ROM includes Reset vector Interrupt vector General pu...

Page 11: ...rnal reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset status from NT0 NP...

Page 12: ...ing example shows the way to define the interrupt vector in the program memory Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is a unique buffer and only one level...

Page 13: ...am User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from buffers RETI End of interrup...

Page 14: ...lookup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z overflow FFH 00 Y Y 1 NOP MOVC To lookup data R...

Page 15: ...ord 16 bits data DW 5105H DW 2012H The other example of look up table is to add Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register by B0ADD ADD in...

Page 16: ...OM boundary B0ADD PCL A PCL PCL ACC PCH 1 when PCL overflow occurs JMP A0POINT ACC 0 jump to A0POINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP A3POINT ACC 3 jump to A3POI...

Page 17: ...table listing is five 0X00FD JMP A0POINT ACC 0 jump to A0POINT 0X00FE JMP A1POINT ACC 1 jump to A1POINT 0X00FF JMP A2POINT ACC 2 jump to A2POINT 0X0100 JMP A3POINT ACC 3 jump to A3POINT 0X0101 JMP A4P...

Page 18: ...end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end of code AAA INCM...

Page 19: ...T0C TC0M TC0C STKP E P0UR P1UR P2UR P5UR YZ P1OC F STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H 2 2 1 2 SYSTEM REGISTER DESCRIPTION R Working register and ROM look up data buffer Y Z Working YZ and...

Page 20: ...R W P2 0D5H P54 R W P5 0D8H T0ENB T0rate2 T0rate1 T0rate0 T0TB R W T0M 0D9H T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 R W T0C 0DAH TC0ENB TC0rate2 TC0rate1 TC0rate0 TC0CKS ALOAD0 TC0OUT PWM0OUT R W TC0M...

Page 21: ...by B0MOV instruction during the instant addressing mode Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Write ACC data f...

Page 22: ...by external Reset Pin Bit 5 LVD36 LVD 3 6V operating flag and only support LVD code option is LVD_H 0 Inactive VDD 3 6V 1 Active VDD 3 6V Bit 4 LVD24 LVD 2 4V operating flag and only support LVD code...

Page 23: ...ONE ADDRESS SKIPPING There are nine instructions CMPRS INCS INCMS DECS DECMS BTS0 BTS1 B0BTS0 B0BTS1 with one address skipping function If the result of these instructions is true the PC will add 2 s...

Page 24: ...0ADD M A instructions for carry to PCH when PCL overflow automatically For jump table or others applications users can calculate PC value by the three instructions and don t care PCL overflow problem...

Page 25: ...AM bank 0 for Y register B0MOV Z 25H To set location 25H for Z register B0MOV A YZ To read a data into ACC Example Uses the Y Z register as data pointer to clear the RAM data B0MOV Y 0 Y 0 bank 0 B0MO...

Page 26: ...gister 2 3 2 DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC Example Move 0x12 RAM location data into ACC B0MOV A 12H To get a content of RAM l...

Page 27: ...ary storage of stack addresses The two stack operations are writing to the top of the stack push and reading from the top of stack pop Push operation decrements the STKP and the pop operation incremen...

Page 28: ...ores the program counter about the op code address The Stack Save operation is as the following table Stack Level STKP Register Stack Buffer Description STKPB1 STKPB0 High Byte Low Byte 0 1 1 Free Fre...

Page 29: ...ction cycle is 16 oscillator clocks Reset_Pin Reset Enable External reset pin P11 Enable P1 1 input only without pull up resister Security Enable Enable ROM code Security function Disable Disable ROM...

Page 30: ...iption 0 0 Watchdog reset Watchdog timer overflow 0 1 Reserved 1 0 Power on reset and LVD reset Power voltage is lower than LVD detecting level 1 1 External reset External reset pin detect low level s...

Page 31: ...em is reset After watchdog reset the system restarts and returns normal mode Watchdog reset sequence is as following Watchdog timer status System checks watchdog timer overflow status If watchdog time...

Page 32: ...riving motor The loading operating induces noise and overlaps with the DC power VDD drops by the noise and the system works under unstable power situation The power on duration and power down duration...

Page 33: ...voltage level For low battery detect application only checking LVD24 LVD36 status to be battery status This is a cheap and easy solution 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PFLAG NT0...

Page 34: ...until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and the system return to normal mode after reset sequence This method also can improve brown out reset con...

Page 35: ...ystem keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is su...

Page 36: ...Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrical Over str...

Page 37: ...rops and the voltage lower than reset pin detect level the system would be reset If want to make the reset active earlier set the R2 R1 and the cap between VDD and C terminal voltage is larger than 0...

Page 38: ...sc Fcpu Flosc 4 CPUM 1 0 XIN XOUT STPHX HOSC Fcpu Code Option Fosc Fosc CLKMD Fcpu HOSC High_Clk code option Fhosc External high speed clock Internal high speed RC clock Flosc Internal low speed RC cl...

Page 39: ...is external low cost RC type oscillator The RC oscillator circuit only connects to XIN pin and the XOUT pin is bi direction GPIO mode 32K X tal The system high speed clock source is external low speed...

Page 40: ...Hz CRYSTAL CERAMIC 32KHz RC Type MCU VCC GND C 20pF XIN XOUT VDD VSS C 20pF CRYSTAL MCU VCC GND C 27pF XIN XOUT VDD VSS C 27pF CRYSTAL R MCU VCC GND XIN XOUT VDD VSS C Note Connect the Crystal Ceramic...

Page 41: ...0 40 00 45 00 2 1 2 5 3 3 1 3 3 3 5 4 4 5 5 5 5 6 6 5 7 VDD V Freq KHz ILRC The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD bit of OSCM register Flosc Inter...

Page 42: ...rnal oscillator operations When STPHX 0 the external oscillator or internal high speed RC type oscillator active When STPHX 1 the external oscillator or internal high speed RC type oscillator are disa...

Page 43: ...on reset LVD reset watchdog reset external reset pin active 64ms Fhosc 32KHz 512us Fhosc 4MHz 128us Fhosc 16MHz Oscillator warm up time of power down mode wake up condition 2048 Fhosc Crystal resonato...

Page 44: ...wn Mode Wake up Timing Wake up Pin Rising Edge Oscillator Fcpu Instruction Cycle Tosp Tost Wake up Pin Falling Edge System inserts into power down mode Edge trigger system wake up Green Mode Wake up T...

Page 45: ...me is depended on oscillator s material factory and architecture Normally the low speed oscillator s start up time is lower than high speed oscillator The RC type oscillator s start up time is faster...

Page 46: ...Block One of reset trigger sources actives One of reset trigger sources actives One of reset trigger sources actives Operating Mode Clock Control Table Operating Mode Normal Mode Slow Mode Green Mode...

Page 47: ...nd full functions are controllable The system rate is low speed Flosc 4 The internal low speed RC type oscillator actives and the high speed oscillator is controlled by STPHX 1 In slow mode to stop hi...

Page 48: ...into green mode After system wake up from green mode the CPUM1 bit is disabled zero status automatically The program stops executing and full functions are disabled Only the timer with wake up functio...

Page 49: ...acro directly Example Switch slow mode to normal mode The external high speed oscillator stops Slow2Normal Declare Slow2Normal macro directly Example Switch normal slow mode to green mode GreenMode De...

Page 50: ...ator clocks as the wakeup time to stable the oscillator circuit After the wakeup time the system goes into the normal mode Note Wakeup from green mode is no wakeup time because the clock doesn t stop...

Page 51: ...evel changing When wake up pin occurs rising edge or falling edge the system is waked up by the trigger edge The Port 0 and Port 1 have wakeup function Port 0 wake up function always enables but the P...

Page 52: ...ut TC0 Time Out Note The GIE bit must enable during all interrupt operation 6 2 INTEN INTERRUPT ENABLE REGISTER INTEN is the interrupt request control register including one internal interrupts one ex...

Page 53: ...INT0 request flag 0 None INT0 interrupt request 1 INT0 interrupt request Bit 4 T0IRQ T0 timer interrupt request flag 0 None T0 interrupt request 1 T0 interrupt request Bit 5 TC0IRQ TC0 timer interrupt...

Page 54: ...s save and load ACC PFLAG data into buffers and avoid main routine error after interrupt service routine finishing Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is...

Page 55: ...ge configuration the trigger edge will be latched and the system executes interrupt service routine fist after wake up 0BFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDGE P00G1 P00G0 Read Write...

Page 56: ...Hz 16 B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 64H Set T0C initial value 64H B0MOV T0C A Set T0 interval 10 ms B0BSET...

Page 57: ...on ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers B0BTS1 FT0IRQ Check T0IRQ JMP EXIT_INT T0IRQ 0 exit interrupt vector T0 interrupt service routine B0...

Page 58: ...R FTC0IEN Disable TC0 interrupt service B0BCLR FTC0ENB Disable TC0 timer MOV A 20H B0MOV TC0M A Set TC0 clock Fcpu 64 MOV A 64H Set TC0C initial value 64H B0MOV TC0C A Set TC0 interval 10 ms B0BSET FT...

Page 59: ...g care of One is to set the priority for these interrupt requests Two is using IEN and IRQ flags to decide which interrupt to be executed Users have to check interrupt control bit and interrupt reques...

Page 60: ...s as following I O Pin Shared Pin Shared Pin Control Condition Name Type Name Type P0 0 I O INT0 DC P00IEN 1 P1 1 I RST DC Reset_Pin code option Reset VPP HV OTP Programming P1 2 I O XOUT AC High_CLK...

Page 61: ...Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2M P25M P24M P23M P22M P21M P20M Read Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5M P54M Re...

Page 62: ...Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P0UR P00R Read Write W After reset 0 0E1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1UR P13R P12R P10R Read Write W W W After reset 0 0 0 0E2H Bit 7 Bit 6 B...

Page 63: ...s pin 0E9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1OC P10OC Read Write W After reset 0 Bit 0 P10OC P1 0 open drain control bit 0 Disable open drain mode 1 Enable open drain mode Example Ena...

Page 64: ...ead Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5 P54 Read Write R W After reset 0 Note The P11 keeps 1 when external reset enable by co...

Page 65: ...In power down mode and green mode the watchdog timer stops Always_On Enable watchdog timer function The watchdog timer actives and not stop in power down mode and green mode In high noisy environment...

Page 66: ...hdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An operation of watchdog timer is as following To clear the watchdog...

Page 67: ...specific time intervals based on the selected clock frequency Interrupt function T0 timer function supports interrupt function When T0 timer occurs overflow the T0IRQ actives and the system points pr...

Page 68: ...Q by program is necessary in interrupt procedure T0 timer can works in normal mode slow mode and green mode In green mode T0 keeps counting set T0IRQ and wakes up system when T0 timer overflows 0x00 o...

Page 69: ...R T0C is T0 8 bit counter When T0C overflow occurs the T0IRQ flag is set as 1 and cleared by program The T0C decides T0 interval time through below equation to calculate a correct value It is necessar...

Page 70: ...egister for T0 Interval time MOV A value B0MOV T0C A Clear T0IRQ B0BCLR FT0IRQ Enable T0 timer and interrupt function B0BSET FT0IEN Enable T0 interrupt function B0BSET FT0ENB Enable T0 timer T0 works...

Page 71: ...ightness adjuster The main purposes of the TC0 timer are as following 8 bit programmable up counting timer Generate time out at specific time intervals based on the selected clock frequency Interrupt...

Page 72: ...upt procedure is system program counter points to interrupt vector ORG 8 and executes interrupt service routine after TC0 overflow occurrence Clear TC0IRQ by program is necessary in interrupt procedur...

Page 73: ...ntrolled by TC0OUT ALOAD0 bits Bit 1 TC0OUT TC0 time out toggle signal output control bit Only valid when PWM0OUT 0 0 Disable P5 4 is I O function 1 Enable P5 4 is output TC0OUT signal Bit 2 ALOAD0 Au...

Page 74: ...C1 TC0C0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TC0C initial value is as following TC0C initial value N TC0 interrupt interval time TC0 clock rate N is...

Page 75: ...DH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC0R TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of TC0R initial value is as...

Page 76: ...al continuous signal rate e g continuous pulse R C type oscillating signal These signal phase don t synchronize with MCU s main clock Use TC0 event to measure it and calculate the signal rate in progr...

Page 77: ...M cycle in PWM mode The PWM0OUT bit must be 0 when buzzer output function works 8 3 8 PULSE WIDTH MODULATION PWM The PWM is duty cycle programmable design to offer various PWM signals When TC0 timer e...

Page 78: ...0000000b 11111111b 0 1 64 0x00 0x3F xx000000b xx111111b 1 0 32 0x00 0x1F xxx00000b xxx11111b 1 1 16 0x00 0x0F xxxx0000b xxxx1111b 1 256 Duty 1 64 Duty 1 32 Duty 1 16 Duty The PWM output pin is shared...

Page 79: ...Q B0BCLR FTC0IRQ Enable TC0 timer and interrupt function B0BSET FTC0IEN Enable TC0 interrupt function B0BSET FTC0ENB Enable TC0 timer TC0 EVENT COUNTER CONFIGURATION Reset TC0 timer MOV A 0x00 Clear T...

Page 80: ...R B0MOV TC0C A B0MOV TC0R A Enable TC0 timer and buzzer output function B0BSET FTC0ENB Enable TC0 timer B0BSET FTC0OUT Enable TC0 buzzer output function TC0 PWM CONFIGURATION Reset TC0 timer MOV A 0x0...

Page 81: ...r M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 N R RRC M A RRC M 1 O RRCM M M RRC M 1 N C RLC M A RLC M 1 E RLCM M M RLC M...

Page 82: ...up resistor disable Vin Vdd 2 uA I O port pull up resistor Rup Vin Vss Vdd 3V 100 200 300 K Vin Vss Vdd 5V 50 100 180 I O output source current IoH Vop Vdd 0 5V 8 15 mA sink current IoL Vop Vss 0 5V...

Page 83: ...APHS The Graphs in this section are for design guidance not tested or guaranteed In some graphs the data presented are outside specified operating range This is for information only and devices are gu...

Page 84: ...e EV KIT provides LVD configuration to emulation To emulate the function must be through EV KIT SN8P2511 2501A B C EV KIT PCB Outline CON1 Connect to SN8ICE 2K Plus II CON1 includes GPIO EV KIT contro...

Page 85: ...II power switch must be turned off before you connect the SN8P2511 2501A B C EV KIT to SN8ICE2K Plus II 2 Connect EV KIT JP6 CON1 to ICE JP3 CON1 3 Turn on SN8ICE2K Plus 2 power switch to start emula...

Page 86: ...TPCLK 5 6 OE ShiftDat DIP 4 4 45 DIP45 D1 7 8 D0 DIP 5 5 44 DIP44 D3 9 10 D2 DIP 6 6 43 DIP43 D5 11 12 D4 DIP 7 7 42 DIP42 D7 13 14 D6 DIP 8 8 41 DIP41 VDD 15 16 VPP DIP 9 9 40 DIP40 HLS 17 18 RST DIP...

Page 87: ...pin text tool Pin Assignment JP1 JP2 Pin Number JP1 JP2 Pin Name IC Pin Number IC Pin Name JP3 Pin Number IC Pin Number IC Pin Name JP3 Pin Number 1 VDD 4 VDD 21 4 5 VDD 20 21 2 GND 11 VSS 28 12 13 V...

Page 88: ...ction line This note listed the production definition of all 8 bit MCU for order or obtain information This definition is only for Blank OTP MCU 13 2 MARKING INDETIFICATION SYSTEM Title SONiX 8 bit MC...

Page 89: ...IP 0 70 Green Package SN8P2511SG OTP 2511 SOP 0 70 Green Package SN8P2511XG OTP 2511 SSOP 0 70 Green Package PB Free Package Name ROM Type Device Package Temperature Material SN8P2511PB OTP 2511 DIP 0...

Page 90: ...14 1 P DIP 14 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 0 735 0 075 0 775 18 669 1 905 19 685 E 0 300 7 62 E1 0 245 0 250 0 255...

Page 91: ...A 0 058 0 064 0 068 1 4732 1 6256 1 7272 A1 0 004 0 010 0 1016 0 254 B 0 013 0 016 0 020 0 3302 0 4064 0 508 C 0 0075 0 008 0 0098 0 1905 0 2032 0 2490 D 0 336 0 341 0 344 8 5344 8 6614 8 7376 E 0 15...

Page 92: ...mm A 0 053 0 069 1 3462 1 7526 A1 0 004 0 010 0 1016 0 254 A2 0 059 1 4986 b 0 008 0 012 0 2032 0 3048 b1 0 008 0 011 0 2032 0 2794 c 0 007 0 010 0 1778 0 254 c1 0 007 0 009 0 1778 0 2286 D 0 189 0 19...

Page 93: ...occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distr...

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