SN8P2501D
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 30
Version 1.5
2.5 CODE OPTION TABLE
The code option is the system hardware configurations including system clock rate, watchdog timer operation, LVD
option, reset pin option and OTP ROM security control. The code option items are as following table:
Code Option
Content
Function Description
Noise_Filter
Enable
Enable Noise Filter and the Fcpu is Fosc/4~Fosc/16.
Disable
Disable Noise Filter and the Fcpu is Fosc/1~Fosc/16.
High_Clk
IHRC_16M
High speed internal 16MHz RC. XIN/XOUT pins are bi-direction GPIO mode.
IHRC_RTC
High speed internal 16MHz RC with 0.5sec RTC. XIN/XOUT pins are
connected to external 32.768KHz crystall.
RC
Low cost RC for external high clock oscillator. XIN pin is connected to RC
oscillator. XOUT pin is bi-direction GPIO mode.
32K X’tal
Low frequency, power saving crystal (e.g. 32.768KHz) for external high
clock oscillator.
12M X’tal
High speed crystal /resonator (e.g. 12MHz) for external high clock oscillator.
4M X’tal
Standard crystal /resonator (e.g. 4M) for external high clock oscillator.
Watch_Dog
Always_On
Watchdog timer is always on enable even in power down and green mode.
Enable
Enable watchdog timer. Watchdog timer stops in power down mode and
green mode.
Disable
Disable Watchdog function.
Fcpu
Fosc/1
Instruction cycle is 1 oscillator clocks.
Noise Filter must be disabled.
Fosc/2
Instruction cycle is 2 oscillator clocks.
Noise Filter must be disabled.
Fosc/4
Instruction cycle is 4 oscillator clocks.
Fosc/8
Instruction cycle is 8 oscillator clocks.
Fosc/16
Instruction cycle is 16 oscillator clocks.
Reset_Pin
Reset
Enable External reset pin.
P11
Enable P1.1 input only without pull-up resister.
Security
Enable
Enable ROM code Security function.
Disable
Disable ROM code Security function.
LVD
LVD_L
LVD will reset chip if VDD is below 2.0V
LVD_M
LVD will reset chip if VDD is below 2.0V
Enable LVD24 bit of PFLAG register for 2.4V low voltage indicator.
LVD_H
LVD will reset chip if VDD is below 2.4V
Enable LVD36 bit of PFLAG register for 3.6V low voltage indicator.
LVD_MAX
LVD will reset chip if VDD is below 3.6V
2.5.1 Fcpu code option
Fcpu means instruction cycle of normal mode (high clock). In slow mode, the system clock source is internal low speed
RC oscillator. The Fcpu of slow mode isn
’t controlled by Fcpu code option and fixed Flosc/4 (16KHz/4 @3V, 32KHz/4
@5V).
2.5.2 Reset_Pin code option
The reset pin is shared with general input only pin controlled by code option.
Reset:
The reset pin is external reset function. When falling edge trigger occurring, the system will be reset.
P11:
Set reset pin to general input only pin (P1.1). The external reset function is disabled and the pin is input pin.
2.5.3 Security code option
Security code option is OTP ROM protection. When enable security code option, the ROM code is secured and not
dumped complete ROM contents.
2.5.4 Noise Filter code option
Noise Filter code option is a power noise filter manner to reduce noisy effect of system clock. If noise filter enable,
Fcpu is limited below Fosc/1 and Fosc/2. The fast Fcpu rate is Fosc/4. If noise filter disable, the Fosc/1 and Fosc/2
options are released. In high noisy environment, enable noise filter, enable watchdog timer and select a good LVD
level can make whole system work well and avoid error event occurrence.
