SONIX SN8P1700 Series User Manual Download

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

SONiX TECHNOLOGY CO., LTD

Page 184

Revision 1.93

CHIP DECLARATION IN ASSEMBLER

Assembler

OTP Device Part Number

MASK Device Part Number

CHIP SN8P1702

SN8P1702

SN8A1702A

CHIP SN8P1704

SN8P1704

SN8A1704A

CHIP SN8P1706

SN8P1706

SN8A1706A

CHIP SN8P1707

SN8P1707

SN8A1707A

CHIP SN8P1708

SN8P1708

SN8A1708A

PROGRAM CHECK LIST

Item

Description

Pull-up Resister

Use @SET_PUR macro to enable or disable on-chip pull-up resisters. Refer I/O port chapter

for detailed information.

Undefined Bits

All bits those are marked as “0” (undefined bits) in system registers should be set “0” to

avoid unpredicted system errors.

ADC

Set ADC input pin I/O direction as input mode and disable pull-up resister of ADC input pin

SIO Master Mode

Set SCK (P5.0) and SO (P5.2) pin as output mode. Set SI (P5.1) pin as input mode.

SIO Slave Mode

Set SO (P5.2) pin as output mode. Set SCK (P5.0) and SI (P5.1) pin as input mode.

PWM0

Set PWM0 (P5.4) pin as output mode.

PWM1

Set PWM1 (P5.3) pin as output mode.

Interrupt

Do not enable interrupt before initializing RAM.

Non-Used I/O

Non-used I/O ports should be pull-up or pull-down in input mode, or be set as low in output

mode to save current consumption.

Sleep Mode

Enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup.

Stack Buffer

Be careful of function call and interrupt service routine operation. Don’t let stack buffer

overflow or underflow.

System Initial

1. Write 0x7F into STKP register to initial stack pointer and disable global interrupt

2. Clear all RAM.

3. Initialize all system register even unused registers.

Noisy Immunity

1. Enable OSG and High_Clk / 2 code option together

2. Enable the watchdog option to protect system crash.

3. Non-used I/O ports should be set as output low mode

4. Constantly refresh important system registers and variables in RAM to avoid system

crash by a high electrical fast transient noise.

5. Enable the LVD option to improve the power on reset or brown-out reset performance

Summary of Contents for SN8P1700 Series

Page 1: ...not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application...

Page 2: ...instruction during the instant addressing mode P38 7 Correct the description of STKnH P40 8 Change special register is located at 08h FFh to special register is located at 80h FFh P47 9 Correct the bi...

Page 3: ...N8P1707 SN8P1708 FEATURES 15 SYSTEM BLOCK DIAGRAM 16 PIN ASSIGNMENT 17 PIN DESCRIPTIONS 22 PIN CIRCUIT DIAGRAMS 22 2 2 2 ADDRESS SPACES 23 PROGRAM MEMORY ROM 23 OVERVIEW 23 USER RESET VECTOR ADDRESS 0...

Page 4: ...PING 44 3 3 3 ADDRESSING MODE 45 OVERVIEW 45 IMMEDIATE ADDRESSING MODE 45 DIRECTLY ADDRESSING MODE 45 INDIRECTLY ADDRESSING MODE 45 TO ACCESS DATA in RAM BANK 0 46 TO ACCESS DATA in RAM BANK 1 46 4 4...

Page 5: ...72 P5M Port 5 Input Output Direction Register 73 INTRQ Interrupt Request Flag Register 74 INTRQ Interrupt Request Flag Register 75 INTRQ Interrupt Request Flag Register 76 INTEN Interrupt Request Con...

Page 6: ...EGISTER DESCRIPTION 103 EXTERNAL HIGH SPEED OSCILLATOR 104 OSCILLATOR MODE CODE OPTION 104 OSCILLATOR DEVIDE BY 2 CODE OPTION 104 OSCILLATOR SAFE GUARD CODE OPTION 104 SYSTEM OSCILLATOR CIRCUITS 105 E...

Page 7: ...FREQUENCY TABLE 123 TIMER COUNTER 1 TC1 125 OVERVIEW 125 TC1M MODE REGISTER 126 TC1C COUNTING REGISTER 127 TC1R AUTO LOAD REGISTER 128 TC1 TIMER COUNTER OPERATION SEQUENCE 129 TC1 CLOCK FREQUENCY OUT...

Page 8: ...148 FALLING EDGE TRANSMITTER RECEIVER MODE 149 RISING EDGE RECEIVER MODE 150 FALLING EDGE RECEIVER MODE 151 SIO SLAVE OPERATING DESCRIPTION 152 RISING EDGE TRANSMITTER RECEIVER MODE 153 FALLING EDGE T...

Page 9: ...CIRCUIT 172 The right placement of bypass capacitors in single VDD case 172 The right placement of bypass capacitors in multiple VDD case 173 GENERAL PCB POWER LAYOUT 174 EXTERNAL OSCILLATOR CIRCUIT 1...

Page 10: ...on 1 93 1 1 17 7 7 ELECTRICAL CHARACTERISTIC 186 ABSOLUTE MAXIMUM RATING 186 STANDARD ELECTRICAL CHARACTERISTIC 186 1 1 18 8 8 PACKAGE INFORMATION 187 P DIP18 PIN 187 SOP18 PIN 188 SSOP20 PIN 189 S DI...

Page 11: ...stack buffers Besides the user can choose desired oscillator configurations for the controller There are four oscillator configurations to select for generating system clock including High Low Speed...

Page 12: ...nputs External high clock RC type up to 10 MHz External high clock Crystal type up to 16 MHz One 8 bit timer counters TC0 Internal low clock RC type 16KHz 3V 32KHz 5V On chip watchdog timer Normal mod...

Page 13: ...t timer counters TC0 TC1 Dual clock system offers three operating modes On chip watchdog timer External high clock RC type up to 10 MHz Eight levels stack buffer External high clock Crystal type up to...

Page 14: ...channel Buzzer output BZ0 BZ1 An 8 bit basic timer T0 Two 8 bit timer counters TC0 TC1 Dual clock system offers three operating modes On chip watchdog timer External high clock RC type up to 10 MHz Ei...

Page 15: ...T0 Two 8 bit timer counters TC0 TC1 Dual clock system offers three operating modes On chip watchdog timer External high clock RC type up to 10 MHz Eight levels stack buffer External high clock Crysta...

Page 16: ...PT CONTROL TIMER COUNTER PORT 0 PORT 2 PORT 1 PORT 4 PORT 5 FLAGS DAC ADC DAO AIN0 AIN7 SIO TX RX Internal CLK PWM1 PWM0 PWM0 Buzzer0 PWM1 Buzzer1 Low Volt Detector Watch Dog Timer PC IR OTP ROM H OSC...

Page 17: ...IN1 8 11 P5 4 BZ0 PWM0 P4 0 AIN0 9 10 VDD SN8P1702P SN8P1702S MASK Type SN8A1702A SOP 18PIN SN8A1702A PDIP 18PIN SN8A1702A SSOP 20PIN P0 0 INT0 1 U 18 VDD RST 2 17 XIN P1 1 3 16 XOUT P1 0 4 15 P5 0 VS...

Page 18: ...P5 0 SCK P4 2 AIN2 10 19 P5 1 SI P4 1 AIN1 11 18 P5 2 SO P4 0 AIN0 12 17 P5 3 BZ1 PWM1 AVREFH 13 16 P5 4 BZ0 PWM0 VDD 14 15 DAO SN8P1704K SN8P1704S MASK Type SN8A1704A SOP 28PIN SN8A1704A SKDIP 28PIN...

Page 19: ...0 20 21 AVREFH SN8P1706P MASK Type SN8A1706A P DIP 40PIN P1 5 1 U 40 RST P1 4 2 39 P0 2 INT2 P1 3 3 38 P0 1 INT1 VDD 4 37 P0 0 INT0 P1 2 5 36 NC P1 1 6 35 XIN P1 0 7 34 XOUT P2 0 8 33 VSS P2 1 9 32 P2...

Page 20: ...AIN6 P4 5 AIN5 P4 4 AIN4 MASK Type SN8A1707A QFP 44PIN XIN XOUT VSS P2 7 P2 6 P2 5 P2 4 P5 0 SCK P5 1 SI P5 2 SO P5 3 BZ1 PWM1 44 43 42 41 40 39 38 37 36 35 34 NC 1 O 33 P5 4 BZ0 PWM0 P0 0 INT0 2 32...

Page 21: ...VSS SN8P1708P SN8P1708X MASK Type SN8A1708A SSOP 48PIN SN8A1708A P DIP 48PIN P2 5 1 U 48 P2 4 P2 6 2 47 P5 0 SCK P2 7 3 46 P5 1 SI VSS 4 45 P5 2 SO VSS 5 44 P5 3 BZ1 PWM1 XOUT 6 43 VSS XIN 7 42 P5 4...

Page 22: ...ort 4 0 Port 4 7 bi direction pins Built in pull up resisters P5 0 SCK I O Port 5 0 bi direction pin and SIO s clock input output Built in pull up resisters P5 1 SI I O Port 5 1 bi direction pin and S...

Page 23: ...ctor addresses 1 word Interrupt vector addresses 5 word reserved area 4K words SN8P1706 SN8P1707 SN8P1708 2K words SN8P1704 1K words SN8P1702 All of the program memory is partitioned into three coding...

Page 24: ...009H User program 000FH 0010H 0011H 07FEH General purpose area End of user program 07FFH Reserved Figure 2 2 ROM Address Structure SN8P1704 ROM 0000H Reset vector User reset vector 0001H Jump to user...

Page 25: ...INTERRUPT VECTOR ADDRESS 0008H A 1 word vector address area is used to execute interrupt request If any interrupt service is executed the program counter PC value is stored in stack buffer and points...

Page 26: ...UF B0XCH doesn t change C Z flag PUSH Push 80H 87H system registers POP Pop 80H 87H system registers B0XCH A ACCBUF RETI End of interrupt service routine ENDP End of program Remark It is easy to get t...

Page 27: ...truction is executed the low byte data of ROM then will be stored in ACC and high byte data stored in R register Example To look up the ROM data located TABLE1 B0MOV Y TABLE1 M To set lookup table1 s...

Page 28: ...iled information Example Increase Y and Z register by B0ADD ADD instruction B0MOV Y TABLE1 M To set lookup table s middle address B0MOV Z TABLE1 L To set lookup table s low address B0MOV A BUF Z Z BUF...

Page 29: ...A3POINT In following example the jump table starts at 0x00FD When execute B0ADD PCL A If ACC 0 or 1 the jump table points to the right address If the ACC is larger then 1 will cause error because PCH...

Page 30: ...A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five JMP A0POINT If ACC 0 jump to A0POINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP A3POINT AC...

Page 31: ...ral purpose area in bank 1 128 8 bit system special register area The memory is separated into bank 0 and bank 1 The user can program RAM bank selection bits of RBANK register to access all data in an...

Page 32: ...AM Location of SN8P1704 RAM location 000h 000h 07Fh of Bank 0 To store general purpose data 128 bytes 07Fh General purpose area 080h 080h 0FFh of Bank 0 To store system registers 128 bytes System regi...

Page 33: ...y Example Access RAM bank 0 in RAM bank 1 BANK 1 B0BSET RBNKS0 Get into RAM bank 1 B0MOV A BUF0 Read BUF0 data BUF0 is in RAM bank0 MOV BUF1 A Write BUF0 data to BUF1 BUF1 is in RAM bank1 MOV A BUF1 R...

Page 34: ...to read write data through ACC The Lower 4 bit of H register is pointed to RAM bank number and L register is pointed to RAM address number respectively The higher 4 bit data of H register is truncate...

Page 35: ...RAM bank 0 It employs Y and Z registers to addressing RAM location in order to read write data through ACC The Lower 4 bit of Y register is pointed to RAM bank number and Z register is pointed to RAM...

Page 36: ...T1 XBIT0 R W R W R W R W R W R W R W R W Note Please consult the LOOK UP TABLE DESCRIPTION about X register look up table application R REGISTERS There are two major functions of the R register First...

Page 37: ...action without borrowing signal or executed rotation instruction with shifting out logic 1 C 0 If executed arithmetic addition without occurring carry signal or executed arithmetic subtraction with bo...

Page 38: ...ory MOV BUF A Write a immediate data into ACC MOV A 0FH Write ACC data from BUF data memory MOV A BUF The PUSH and POP instructions don t store ACC value as any interrupt service executed ACC must be...

Page 39: ...m counter PC data Figure 2 7 Stack Save and Stack Restore Operation STACK BUFFER STK7H STK6H STK5H STK4H STK3H STK2H STK1H STK0H STK7L STK6L STK5L STK4L STK3L STK2L STK1L STK0L STKP 0 STKP 1 STKP 2 ST...

Page 40: ...Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 STKP stack pointer initial value 0xxx 1111...

Page 41: ...0 1 0 STK5H STK5L 6 1 0 0 1 STK6H STK6L 7 1 0 0 0 STK7H STK7L 8 Stack Overflow Table 2 1 STKP STKnH and STKnL relative of Stack Save Operation There is a Stack Restore operation corresponding each pus...

Page 42: ...ion Besides it can be replaced with specific address by executing CALL or JMP instruction When JMP or CALL instruction is executed the destination address will be inserted to bit 0 bit 11 PC Initial v...

Page 43: ...C1STEP Else jump to C1STEP C1STEP NOP If the ACC is equal to the immediate data or memory the PC will add 2 steps to skip next instruction CMPRS A 12H Skip next instruction if ACC 12H JMP C0STEP Else...

Page 44: ...ignal occurs after execution of ADD PCL A the carry signal will not affect PCH register Example If PC 0323H PCH 03H PCL 23H PC 0323H MOV A 28H B0MOV PCL A Jump to address 0328H PC 0328H MOV A 00H B0MO...

Page 45: ...addressing mode B0MOV A 12H To get a content of location 12H of bank 0 and save in ACC INDIRECTLY ADDRESSING MODE The indirectly addressing mode is to set up an address in data pointer registers Y Z...

Page 46: ...addressing mode with YZ register CLR Y To clear Y register for accessing RAM bank 0 B0MOV Z 12H To set an immediate data 12H into Z register B0MOV A YZ Use data pointer YZ reads a data from RAM locat...

Page 47: ...K 0 or the bank 0 read write instruction B0MOV B0BSET B0BCLR SYSTEM REGISTER ARRANGEMENT BANK 0 BYTES of SYSTEM REGISTER SN8P1702 0 1 2 3 4 5 6 7 8 9 A B C D E F 8 R Z Y PFLAG 9 A B ADM ADB ADR C P1W...

Page 48: ...de control register SIOR SIO s clock reload buffer SIOB SIO s data buffer P1W Port 1 wakeup register PnM Port n input output mode register Pn Port n data buffer INTRQ Interrupts request register INTEN...

Page 49: ...PC6 PC5 PC4 PC3 PC2 PC1 PC0 R W PCL 0CFH PC10 PC9 PC8 R W PCH 0D0H P00 R P0 data buffer 0D1H P11 P10 R W P1 data buffer 0D4H P43 P42 P41 P40 R W P4 data buffer 0D5H P54 P53 P52 P51 P50 R W P5 data buf...

Page 50: ...7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R W PCL 0CFH PC11 PC10 PC9 PC8 R W PCH 0D0H P02 P01 P00 R P0 data buffer 0D1H P14 P13 P12 P11 P10 R W P1 data bu...

Page 51: ...H TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R W PCL 0CFH PC11 PC10 PC9 PC8 R W PCH 0D0H P02 P01 P00 R P0 data buffer 0D1H P15 P14 P13 P12 P11 P10 R W...

Page 52: ...TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R W PCL 0CFH PC11 PC10 PC9 PC8 R W PCH 0D0H P02 P01 P00 R P0 data buffer 0D1H P15 P14 P13 P12 P11 P10 R W P1...

Page 53: ...ESCRIPTION L Working Register Register Name L Address 080H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 Read Write R W R W R W R W R W...

Page 54: ...rking Register Register Name H Address 081H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBIT0 Read Write R W R W R W R W R W R W R W R W In...

Page 55: ...r Register Name R Address 082H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read Write R W R W R W R W R W R W R W R W Initial Value 0...

Page 56: ...ame Z Address 083H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0...

Page 57: ...Y Address 084H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0...

Page 58: ...me X Address 085H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name XBIT7 XBIT6 XBIT5 XBIT4 XBIT3 XBIT2 XBIT1 XBIT0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0...

Page 59: ...rotation instruction with shifting out logic 0 1 Executed arithmetic addition with occurring carry signal Executed arithmetic subtraction without borrowing signal Executed rotation instruction with sh...

Page 60: ...LTD Page 60 Revision 1 93 RBANK RAM Bank Selection Register Name RBANK Address 087H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name 0 0 0 0 0 0 0 RBNKS0 Read Write R W Initial Value 0 B...

Page 61: ...0 Bit s Name DAENB DAB6 DAB5 DAB4 DAB3 DAB2 DAB1 DAB0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 DAENB DAC Converter Control Bit 0 DAC disable 1 DAC enable DAB6 DAB0 DAC...

Page 62: ...rite R W R W R W R W 0 R W R W Initial Value 0 0 0 0 0 0 0 Bit2 0 Always write zero Bit3 Undefined ADENB ADC Converter Control Bit 0 ADC disable 1 ADC enable ADS ADC Converter Start Bit 0 Stop ADC con...

Page 63: ...CHS0 Read Write R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 Bit3 Undefined ADENB ADC Converter Control Bit 0 ADC disable 1 ADC enable ADS ADC Converter Start Bit 0 Stop ADC converting 1 S...

Page 64: ...t4 bit11 Register Name ADB Address 0B2H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 Read Write R R R R R R R R Initial Value 0 0 0 0 0 0 0...

Page 65: ...3 Bit 2 Bit 1 Bit 0 Bit s Name ADCKS ADLEN 0 ADB3 ADB2 ADB1 ADB0 Read Write R W R W R R R R Initial Value 0 0 0 0 0 0 Bit4 0 Always write zero Bit7 Undefined ADLEN ADC s Resolution Select Bit 0 8 bit...

Page 66: ...IOM must be set to 0 during SIO operating SENB SIO Transceiver Control Bit 0 SIO transceiver disable P5 0 P5 2 are general purpose pins 1 SIO transceiver enable P5 0 P5 2 are SIO pins START SIO Start...

Page 67: ...Register Name SIOR Address 0B5H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name SIOR7 SIOR6 SIOR5 SIOR4 SIOR3 SIOR2 SIOR1 SIOR0 Read Write W W W W W W W W Initial Value 0 0 0 0 0 0 0 0...

Page 68: ...SIOB SIO s Data Buffer Register Name SIOB Address 0B6H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name SIOB7 SIOB6 SIOB5 SIOB4 SIOB3 SIOB2 SIOB1 SIOB0 Read Write R W R W R W R W R W R...

Page 69: ...P1W Address 0C0H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name 0 0 0 P14W P13W P12W P11W P10W Read Write W W W W W Initial Value Bit5 Bit7 0 Always write zero P14W P10W Bit 4 Bit0 of...

Page 70: ...p1 0 as output pin by the bit set instruction SN8P1704 Register Name P1M Address 0C1H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name 0 0 0 P14M P13M P12M P11M P10M Read Write R W R W...

Page 71: ...Bit5 Bit7 0 Always write zero P24M P20M Bit 4 Bit0 of Port 2 Input Output Direction Control Bit 0 Set P2 4 P2 0 to input direction 1 Set P2 4 P2 0 to output direction SN8P1707 SN8P1708 Register Name...

Page 72: ...egister Name P4M Address 0C4H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name P47M P46M P45M P44M P43M P42M P41M P40M Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0...

Page 73: ...egister Name P5M Address 0C5H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name P57M P56M P55M P54M P53M P52M P51M P50M Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0...

Page 74: ...INTRQ Address 0C8H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name 0 0 TC0IRQ 0 0 0 0 P00IRQ Read Write R W R W Initial Value 0 0 Bit4 Bit1 Bit6 Bit7 0 Always write zero TC0IRQ TC0 Int...

Page 75: ...Bit4 Bit7 0 Always write zero TC1IRQ TC1 Interrupt Request Flag 0 No interrupt Request 1 Occur Interrupt Request TC0IRQ TC0 Interrupt Request Flag 0 No interrupt Request 1 Occur Interrupt Request SIO...

Page 76: ...ro TC1IRQ TC1 Interrupt Request Flag 0 No interrupt Request 1 Occur Interrupt Request TC0IRQ TC0 Interrupt Request Flag 0 No interrupt Request 1 Occur Interrupt Request T0IRQ T0 Interrupt Request Flag...

Page 77: ...s 0C9H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name 0 0 TC0IEN 0 0 0 0 P00IEN Read Write R W R W Initial Value 0 0 Bit4 Bit1 Bit6 Bit7 Undefined 0 Always write zero TC0IEN TC0 Interr...

Page 78: ...te zero TC1IEN TC1 Interrupt Request Control Bit 0 Disable interrupt Request 1 Enable Interrupt Request TC0IEN TC0 Interrupt Request Control Bit 0 Disable interrupt Request 1 Enable Interrupt Request...

Page 79: ...trol Bit 0 Disable interrupt Request 1 Enable Interrupt Request TC0IEN TC0 Interrupt Request Control Bit 0 Disable interrupt Request 1 Enable Interrupt Request T0IEN T0 Interrupt Request Control Bit 0...

Page 80: ...ndefined 0 Always write zero WDRST Watchdog Timer Reset Control Bit 0 WDT free run 1 Clear watchdog timer s counter WDRATE WDT s Rate Select Bit 0 14th Watchdog over flow time 1 Fcpu 214 16 1 8th Watc...

Page 81: ...auto load function ALOAD0 1 Under TC0OUT and PWM0OUT applications users must enable and set the TC0R register The main purpose of TC0R is as following Store the auto reload value and set into TC0C wh...

Page 82: ...1 93 PCL Program Counter Low Byte Register Register Name PCL Address 0CEH Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Read Write R W R W R W R W R W...

Page 83: ...D Page 83 Revision 1 93 PCH Program Counter High Byte Register Register Name PCH Address 0CFH Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name PC11 PC10 PC9 PC8 Read Write R W R W R W R...

Page 84: ...terrupt function and wakeup function when the pin get a falling edge Notice Check the design note for the SN8P1702 sleep mode setting SN8P1704 SN8P1706 SN8P1707 SN8P1708 Register Name P0 Address 0D0H...

Page 85: ...P12 P11 P10 Read Write R W R W R W R W R W Initial Value 0 0 0 0 0 Bit5 Bit7 Undefined P10 P14 P1 0 P1 4 Data Buffer 0 Data 0 1 Data 1 SN8P1706 SN8P1707 SN8P1708 Register Name P1 Address 0D1H Bit Bit...

Page 86: ...0 Bit s Name P27 P26 P25 P24 P23 P22 P21 P20 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 P20 P27 P2 0 P2 7 Data Buffer 0 Data 0 1 Data 1 Note In input direction the read i...

Page 87: ...me P44 P43 P42 P41 P40 Read Write R W R W R W R W R W Initial Value 0 0 0 0 0 Bit5 Bit7 Undefined P40 P44 P4 0 P4 4 Data Buffer 0 Data 0 1 Data 1 SN8P1706 SN8P1707 SN8P1708 Register Name P4 Address 0D...

Page 88: ...5 Data Buffer 0 Data 0 1 Data 1 SN8P1706 SN8P1707 SN8P1708 Register Name P5 Address 0D5H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name P57 P56 P55 P54 P53 P52 P51 P50 Read Write R W...

Page 89: ...Bit 1 Bit 0 Bit s Name T0ENB T0rate2 T0rate1 T0rate0 0 0 0 0 Read Write R W R W R W R W Initial Value 0 0 0 0 Bit0 Bit3 Undefined 0 Always write zero T0ENB T0 Timer Control Bit 0 Disable T0 and T0 tim...

Page 90: ...ter value The equation of T0C is as following T0C initial value 256 T0 interrupt interval time input clock The input clock is controlled by T0rate0 T0rate2 bits The T0 interrupt interval time is user...

Page 91: ...o count TC0rate2 TC0rate0 TC0 s Clock Source Select Bits 000 Fcpu 256 001 Fcpu 128 010 Fcpu 64 011 Fcpu 32 100 Fcpu 16 101 Fcpu 8 110 Fcpu 4 111 Fcpu 2 ALOAD0 TC0 Auto Reload Function Control Bit 0 Di...

Page 92: ...unter value The equation of TC0C is as following TC0C initial value 256 TC0 interrupt interval time input clock The input clock is controlled by TC0rate0 TC0rate2 bits The TC0 interrupt interval time...

Page 93: ...o count TC1rate2 TC1rate0 TC1 s Clock Source Select Bits 000 Fcpu 256 001 Fcpu 128 010 Fcpu 64 011 Fcpu 32 100 Fcpu 16 101 Fcpu 8 110 Fcpu 4 111 Fcpu 2 ALOAD1 TC1 Auto Reload Function Control Bit 0 Di...

Page 94: ...unter value The equation of TC1C is as following TC1C initial value 256 TC1 interrupt interval time input clock The input clock is controlled by TC1rate0 TC1rate2 bits The TC1 interrupt interval time...

Page 95: ...n TC1R s value applies to TC1OUT and PWM1OUT functions The TC1R operation needs to enable TC1 auto load function ALOAD1 1 Under TC1OUT and PWM1OUT applications users must enable and set the TC1R regis...

Page 96: ...ad Write R W R W R W R W R W Initial Value 0 1 1 1 1 Bit4 Bit6 Undefined GIE Global Interrupt Control Bit 0 Disable all interrupt service request 1 Enable interrupt service request STKPB0 STKPB3 Stack...

Page 97: ...gister Name HL Address 0E6H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name HL7 HL6 HL5 HL4 HL3 HL2 HL1 HL0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Func...

Page 98: ...gister Name YZ Address 0E7H Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit s Name YZ7 YZ6 YZ5 YZ4 YZ3 YZ2 YZ1 YZ0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Func...

Page 99: ...C circuit connecting to the reset pin The low voltage detector LVD is built in internal circuit When one of the reset devices occurs the system will reset and the system registers become initial value...

Page 100: ...sers can use an external reset circuit to control system operation It is necessary that the VDD must be stable External Reset VDD Internal Reset Signal External Reset Detect Level End of External Rese...

Page 101: ...LVD DESCRIPTION The LVD is a low voltage detector It detects VDD level and reset the system as the VDD lower than the desired voltage The detect level is 2 4V If the VDD lower than 2 4V the system res...

Page 102: ...e SIO AD converter PWM output PWM0 PWM1 Buzzer output TC0OUT TC1OUT CLOCK BLOCK DIAGRAM fl CPUM0 LXOSC fcpu fosc 4 CPUM0 fh HXOSC XIN XOUT STPHX HXRC CPUM0 Divided by 4 CLKMD Divided by 2 OSG Divided...

Page 103: ...3 Bit 2 Bit 1 Bit 0 OSCM 0 WDRST Wdrate 0 CPUM0 CLKMD STPHX 0 R W R W R W R W R W STPHX Eternal high speed oscillator control bit 0 free run 1 stop This bit just only controls external high speed osci...

Page 104: ...requencies High speed crystal needs more current but the low one doesn t For crystals there are three steps to select If the oscillator is RC type to select RC and the system will divide the frequency...

Page 105: ...of external oscillator circuit must be from the micro controller Don t connect them from the neighbor power terminal Note2 The external clock input mode can select RC type oscillator or crystal type...

Page 106: ...cy is Fcpu The other measures the external RC frequency by instruction cycle Fcpu The external RC frequency is the Fcpu multiplied by 4 We can get the Fosc frequency of external RC from the Fcpu frequ...

Page 107: ...is affected by the voltage and temperature of the system In common condition the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V The relative between the RC frequency and voltage...

Page 108: ...e instruction cycle is 3 58MHz 4 895KHz All software and hardware are executed and working In normal mode system can get into power down mode and slow mode SLOW MODE In slow mode the system clock sour...

Page 109: ...t circuit active CPUM0 01 CLKMD 0 CLKMD 1 Figure 6 6 SN8P1700 System Mode Block Diagram Operating mode description MODE NORMAL SLOW POWER DOWN SLEEP REMARK HX osc Running By STPHX Stop LX osc Running...

Page 110: ...slow mode B0BSET FCLKMD To set CLKMD 1 Change the system into slow mode B0BSET FSTPHX To stop external high speed oscillator for power saving Switch slow mode to normal mode If external high clock sto...

Page 111: ...oscillator clocks to be the wakeup time for warming up the oscillator circuit After the wakeup time the system goes into the normal mode The value of the wakeup time is as following The wakeup time 1...

Page 112: ...rate control bits of OSCM register The watchdog timer will be disabled at green and power down modes OSCM initial value 0000 000x 0CAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSCM 0 WDRST Wdra...

Page 113: ...d only used the high nibble By loading different value into the T0M register users can modify the basic timer clock dynamically as program executing Eight rates for T0 timer can be selected by T0RATE0...

Page 114: ...Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T0C T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 R W R W R W R W R W R W R W R W High speed mode fcpu 3 58MHz 4 Low speed mode fcpu 32768Hz 4 T0RATE T0CLOCK Max overflow...

Page 115: ...n Example Setup the T0M and T0C B0BCLR FT0IEN To disable T0 interrupt service B0BCLR FT0ENB To disable T0 timer MOV A 20H B0MOV T0M A To set T0 clock fcpu 64 MOV A 74H B0MOV T0C A To set T0C initial v...

Page 116: ...poses of the TC0 timer counter is as following 8 bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency Arbitrary frequency output Buzzer output O...

Page 117: ...0 0DAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC0M TC0ENB TC0RATE2 TC0RATE1 TC0RATE0 0 ALOAD0 TC0OUT PWM0OUT R W R W R W R W R W R W R W TC0ENB TC0 counter BZ0 PWM0OUT enable bit 0 disable 1...

Page 118: ...0C3 TC0C2 TC0C1 TC0C0 R W R W R W R W R W R W R W R W High speed mode fcpu 3 58MHz 4 Low speed mode fcpu 32768Hz 4 TC0RATE TC0CLOCK Max overflow interval One step max 256 Max overflow interval One ste...

Page 119: ...enable and set the TC0R register The main purpose of TC0R is as following Store the auto reload value and set into TC0C when the TC0C overflow ALOAD0 1 Store the duty value of PWM0OUT function TC0R i...

Page 120: ...auto reload function B0BCLR FTC0IEN To disable TC0 interrupt service B0BCLR FTC0ENB To disable TC0 timer MOV A 20H B0MOV TC0M A To set TC0 clock fcpu 64 MOV A 74H To set TC0C initial value 74H B0MOV T...

Page 121: ...upt service routine JMP EXIT_INT End of TC0 interrupt service routine and exit interrupt vector EXIT_INT POP Pop B0XCH A ACCBUF Restore ACC value RETI Exit interrupt vector Example TC0 interrupt servi...

Page 122: ...zzer output to output multi frequency Figure 7 5 The TC0OUT Pulse Frequency Example Setup TC0OUT output from TC0 to TC0OUT P5 4 The external high speed clock is 4MHz The TC0OUT frequency is 1KHz Becau...

Page 123: ...11 134 0 5123 190 0 9470 246 6 2500 23 0 2682 79 0 3531 135 0 5165 191 0 9615 247 6 9444 24 0 2694 80 0 3551 136 0 5208 192 0 9766 248 7 8125 25 0 2706 81 0 3571 137 0 5252 193 0 9921 249 8 9286 26 0...

Page 124: ...2 0492 190 3 7879 246 25 0000 23 1 0730 79 1 4124 135 2 0661 191 3 8462 247 27 7778 24 1 0776 80 1 4205 136 2 0833 192 3 9063 248 31 2500 25 1 0823 81 1 4286 137 2 1008 193 3 9683 249 35 7143 26 1 087...

Page 125: ...he main purposes of the TC1 timer is as following 8 bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency Arbitrary frequency output Buzzer outpu...

Page 126: ...ervals TC1M initial value 0000 0000 0DCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1M TC1ENB TC1RATE2 TC1RATE1 TC1RATE0 0 ALOAD1 TC1OUT PWM1OUT R W R W R W R W R W R W R W TC1ENB TC1 counter B...

Page 127: ...R W R W R W R W R W R W R W The interval time of TC1 basic timer table High speed mode fcpu 3 58MHz 4 Low speed mode fcpu 32768Hz 4 TC1RATE TC1CLOC K Max overflow interval One step max 256 Max overflo...

Page 128: ...enable and set the TC1R register The main purpose of TC1R is as following Store the auto reload value and set into TC1C when the TC1C overflow ALOAD1 1 Store the duty value of PWM1OUT function TC1R i...

Page 129: ...reload function B0BCLR FTC1IEN To disable TC1 interrupt service B0BCLR FTC1ENB To disable TC1 timer MOV A 20H B0MOV TC1M A To set TC1 clock fcpu 64 MOV A 74H To set TC1C initial value 74H B0MOV TC1C A...

Page 130: ...upt service routine JMP EXIT_INT End of TC1 interrupt service routine and exit interrupt vector EXIT_INT POP Pop B0XCH A ACCBUF Restore ACC value RETI Exit interrupt vector Example TC1 interrupt servi...

Page 131: ...UT Pulse Frequency Example Setup TC1OUT output from TC1 to TC1OUT P5 3 The external high speed clock is 4MHz The TC1OUT frequency is 1KHz Because the TC1OUT signal is divided by 2 set the TC1 clock to...

Page 132: ...ack to 00H the PWM output is forced to high level The pulse width ratio duty cycle is defined by the contents of the reference register TC0R TC1R and is programmed in increments of 1 256 The 8 bit PWM...

Page 133: ...ut to P5 4 and disable P5 4 I O function B0BSET FTC0ENB Enable TC0 timer Note1 The TC0R and TC1R are write only registers Don t process them using INCMS DECMS instructions Example Modify TC0R TC1R reg...

Page 134: ...terrupt service exits the GIE bit will set to 1 to accept the next interrupts request All of the interrupt request signals are stored in INTRQ register The user can program the chip to check INTRQ s c...

Page 135: ...ble 1 enable TC0IEN Timer interrupt control bit 0 disable 1 enable TC1IEN Timer interrupt control bit 0 disable 1 enable INTRQ INTERRUPT REQUEST REGISTER INTRQ is the interrupt request flag register T...

Page 136: ...fter the GIE 1 It is necessary for interrupt service request One of the interrupt requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 level STKP initial...

Page 137: ...oesn t change C Z flag PUSH Push B0BTS1 FP00IRQ Check P00IRQ JMP EXIT_INT P00IRQ 0 exit interrupt vector B0BCLR FP00IRQ Reset P00IRQ INT0 interrupt service routine EXIT_INT POP Pop B0XCH A ACCBUF Rest...

Page 138: ...ble or disable If the P02IEN 1 the trigger event will make the P02IRQ to be 1 and the system enter interrupt vector If the P02IEN 0 the trigger event will make the P02IRQ to be 1 but the system will n...

Page 139: ...t request setup B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 74H Set T0C initial value 74H B0MOV T0C A Set T0 interval 10...

Page 140: ...st setup B0BCLR FTC0IEN Disable TC0 interrupt service B0BCLR FTC0ENB Disable TC0 timer MOV A 20H B0MOV TC0M A Set TC0 clock Fcpu 64 MOV A 74H Set TC0C initial value 74H B0MOV TC0C A Set TC0 interval 1...

Page 141: ...t setup B0BCLR FTC1IEN Disable TC1 interrupt service B0BCLR FT C1ENB Disable TC1 timer MOV A 20H B0MOV TC1M A Set TC1 clock Fcpu 64 MOV A 74H Set TC1C initial value 74H B0MOV TC1C A Set TC1 interval 1...

Page 142: ...will not enter interrupt vector Users need to care for the operation under multi interrupt situation Example SIO interrupt request setup B0BSET FSIOIEN Enable SIO interrupt service B0BCLR FSIOIRQ Cle...

Page 143: ...nterrupt enable Just only any the event occurs and the IRQ will be logic 1 The IRQ and its trigger event relationship is as the below table Interrupt Name Trigger Event Description P00IRQ P0 0 trigger...

Page 144: ...K Jump check to next interrupt B0BTS0 FP02IRQ Check P02IRQ JMP INTP02 Jump to INT2 interrupt service routine INTT0CHK Check T0 interrupt request B0BTS1 FT0IEN Check T0IEN JMP INTTC0CHK Jump check to n...

Page 145: ...n The 3 bit I O counter can monitor the operation of SIO and announce an interrupt request after transmitting receiving 8 bits data After transferring 8 bit data this circuit will be disabled automati...

Page 146: ...SIO pins START SIO progress control bit 0 End of transfer 1 progressing SRATE1 0 SIO s transfer rate select bit 00 fcpu 01 fcpu 32 10 fcpu 16 11 fcpu 8 SCKMD SIO s clock mode select bit 0 internal 1 e...

Page 147: ...H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIOR X X X X X X X X W W W W W W W W The SIOR is designed for the SIO counter to reload the counted value when end of counting It is like a post scale...

Page 148: ...DATA Load transmitted data into SIOB register B0MOV SIOB A MOV A 0FFH Set SIO clock with auto reload function B0MOV SIOR A MOV A 10000011B Setup SIOM and enable SIO function Rising edge B0MOV SIOM A B...

Page 149: ...h auto reload function B0MOV SIOR A MOV A 10000001B Setup SIOM and enable SIO function Falling edge B0MOV SIOM A B0BSET FSTART Start transfer and receiving SIO data CHK_END B0BTS0 FSTART Wait the end...

Page 150: ...B0MOV SIOR A MOV A 10000010B Setup SIOM and enable SIO function Rising edge B0MOV SIOM A B0BSET FSTART Start receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV A...

Page 151: ...B0MOV SIOR A MOV A 10000000B Setup SIOM and enable SIO function Falling edge B0MOV SIOM A B0BSET FSTART Start receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV...

Page 152: ...n 12 bit ADC SONiX TECHNOLOGY CO LTD Page 152 Revision 1 93 SIO SLAVE OPERATING DESCRIPTION Under slave receiver situation the SCK has four phases as following SCK4 SCK3 SCK2 SCK1 Figure 9 8 The Four...

Page 153: ...ction Rising edge B0MOV SIOM A B0BSET FSTART Start transfer and receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV A SIOB Save SIOB data into RXDATA buffer MOV RX...

Page 154: ...tion Falling edge B0MOV SIOM A B0BSET FSTART Start transfer and receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV A SIOB Save SIOB data into RXDATA buffer MOV RX...

Page 155: ...ge B0MOV SIOM A B0BSET FSTART Start receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV A SIOB Save SIOB data into RXDATA buffer MOV RXDATA A LSB DI6 MSB RX data S...

Page 156: ...dge B0MOV SIOM A B0BSET FSTART Start receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV A SIOB Save SIOB data into RXDATA buffer MOV RXDATA A DI5 DI4 RX data DI3...

Page 157: ...occurring There is a example for the application as following Example SIO interrupt demo routine Main MOV A 10000100B Setup SIOM and enable SIO function Falling edge B0MOV SIOM A B0BSET FSTART Start t...

Page 158: ...of I O port is selected by PnM register and a macro SET_PUR is defined for user setting pull up register After the system resets all ports work as input function without pull up resistors Figure 10 1...

Page 159: ...ction P1 0 P1 5 I O Wakeup for power down mode P2 0 P2 7 I O General purpose input output function General purpose input output function P4 0 P4 7 I O ADC analog signal input General purpose input out...

Page 160: ...ble Pull up Fixed 0 Fixed 0 1 1 Fixed 0 Fixed 0 1 1 SN8P1706 SN8P1707 SN8P1708 SET_PUR VAL I O Port Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 VAL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit...

Page 161: ...e 1 output mode P4M initial value 0000 0000 0C4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4M P47M P46M P45M P44M P43M P42M P41M P40M R W R W R W R W R W R W R W R W P40M P47M P4 0 P4 7 I O dir...

Page 162: ...e 162 Revision 1 93 Example I O mode selecting CLR P1M Set all ports to be input mode CLR P2M CLR P4M CLR P5M MOV A 0FFH Set all ports to be output mode B0MOV P1M A B0MOV P2M A B0MOV P4M A B0MOV P5M A...

Page 163: ...1 P20 R W R W R W R W R W R W R W R W P4 initial value 0000 0000 0D4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4 P47 P46 P45 P44 P43 P42 P41 P40 R W R W R W R W R W R W R W R W P5 initial valu...

Page 164: ...OLOGY CO LTD Page 164 Revision 1 93 Example Write one bit data to output port B0BSET P1 3 Set P1 3 and P4 0 to be 1 B0BSET P4 0 B0BCLR P2 3 Set P2 3 and P5 5 to be 0 B0BCLR P5 5 Example Port bit test...

Page 165: ...in ADB register This ADC circuit can select between 8 bit and 12 bit resolution operation by programming ADLEN bit in ADR register A D CONVERTER ADC DATA BUS 8 12 AIN0 P4 0 AIN5 P4 5 AIN2 P4 2 AIN3 P...

Page 166: ...0B3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADR ADCKS ADLEN 0 ADB3 ADB2 ADB1 ADB0 R W R W R R R R ADBn ADC data buffer ADB11 ADB4 bits for 8 bit ADC ADB11 ADB0 bits for 12 bit ADC ADLEN ADC s...

Page 167: ...applications users maybe need more than 8 bit resolution but less than 12 bit ADC converter To process the ADB and ADR data can make the job well First the AD resolution must be set 12 bit mode and th...

Page 168: ...13 4 us 0 fosc 16 1 3 58MHz 16 4 16 286 us 1 12 bit 1 fosc 1 3 58MHz 4 16 17 9 us Example To set AIN0 AIN1 for ADC input and executing 12 bit ADC ADC0 MOV A 60H B0MOV ADR A To set 12 bit ADC and ADC c...

Page 169: ...and AVREFH Circuit of AD Converter Note The capacitor between AIN and GND is a bypass capacitor It is helpful to stable the analog signal Users can omit it VDD AVREF AIN0 P40 Analog Signal Input 0 1u...

Page 170: ...DAO OUTPUT Figure 12 1 The DA converter Block Diagram In order to get a proper linear output a Loading Resistor RL is usually added between DAO and Ground The example shows the result of Vdd 5V RL 150...

Page 171: ...bits Example Output 1 2 VDD from DAO pin MOV A 00111111B B0MOV DAM A Set DAB to a half of the full scale B0BSET FDAENB Enable D A function The DAB s data v s DAO s output voltage as following DAB6 DAB...

Page 172: ...rwise the MCU operation could be affected by noise through power plane Connect appropriate bypass capacitors between VDD and VSS can reform noise influence and get a better power source In general spe...

Page 173: ...r source In normal condition the bypass capacitors are 0 1uF and 1u 47uF The 0 1uF capacitor is necessary and the 1u 47uF capacitor is set better The bypass capacitors should been approached to the mi...

Page 174: ...ltage or external noise through the power line and make the power not stable The power changing may let the system operating error or fail To separate the PCB to different area is a good solution and...

Page 175: ...xternal clock needs to connect two 20pF bypass capacitor from XIN and XOUT pin of micro controller to VSS The two terminals of crystal ceramic resonator connect to XIN and XOUT pin of micro controller...

Page 176: ...e external clock needs to connect one 0 1uF bypass capacitor from XIN of micro controller to VSS The VSS of the bypass capacitor must been connected to the VSS pin of micro controller first It is nece...

Page 177: ...s a simple RC circuit The resistor is set between VDD and RST pin of the micro controller The bypass capacitance is between RST pin and VSS of the micro controller The VDD and VSS of the reset circuit...

Page 178: ...OSG Disable Disable Oscillator Safe Guard function Enable Enable Watch Dog function Watch_Dog Disable Disable Watch Dog function Enable Enable the low voltage detect LVD Disable Disable the low volta...

Page 179: ...macro file INCLUDESTD MACRO1 H INCLUDESTD MACRO2 H INCLUDESTD MACRO3 H list Enable the listing function Constants Definition ONE EQU 1 Variables Definition DATA org 0h Bank 0 data section start from...

Page 180: ...nterrupt b0mov PFLAG 00h pflag x x x x x c dc z b0mov RBANK 00h Set initial RAM bank in bank 0 mov A 40h Clear watchdog timer and initial system mode b0mov OSCM A call ClrRAM Clear RAM call SysInit Sy...

Page 181: ...registers b0xch A AccBuf B0xch instruction do not change C Z flag push Remark this line in SN8P1702 registers Save 80h 87h system Following two lines for SN8X1702 only b0mov A PFLAG b0mov PflagBuf A C...

Page 182: ...pop Remark this line in SN8P1702 Restore 80h 87h system registers b0xch A AccBuf B0xch instruction do not change C Z flag reti Exit the interrupt routine INT0 interrupt service routine P00isr b0bclr F...

Page 183: ...0 clr Y Select bank 0 b0mov Z 0x7f Set YZ address from 7fh ClrRAM10 clr YZ Clear YZ content decms Z z z 1 skip next if z 0 jmp ClrRAM10 clr YZ Clear address 0x00 RAM Bank 1 mov A 1 b0mov Y A Select ba...

Page 184: ...K P5 0 and SI P5 1 pin as input mode PWM0 Set PWM0 P5 4 pin as output mode PWM1 Set PWM1 P5 3 pin as output mode Interrupt Do not enable interrupt before initializing RAM Non Used I O Non used I O por...

Page 185: ...XOR A M A A xor M 1 XOR M A M A xor M 1 XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 R RRC M A RRC M 1 O RRCM M M RRC M 1 C RLC M A RLC M 1 E RLCM...

Page 186: ...ns except those specified below 0 7Vdd Vdd V ViH2 Input with Schmitt trigger buffer Port0 0 8Vdd Vdd V ViH3 Reset pin Xin in RC mode 0 9Vdd Vdd V Input High Voltage ViH4 Xin in X tal mode 0 7Vdd Vdd V...

Page 187: ...NiX TECHNOLOGY CO LTD Page 187 Revision 1 93 1 1 18 8 8PACKAGE INFORMATION P DIP18 PIN Symbols MIN NOR MAX A 0 210 A1 0 015 A2 0 125 0 130 0 135 D 0 880 0 900 0 920 E 0 300BSC E1 0 245 0 250 0 255 L 0...

Page 188: ...it micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 188 Revision 1 93 SOP18 PIN Symbols MIN MAX A 0 093 0 104 A1 0 004 0 012 D 0 447 0 463 E 0 291 0 299 H 0 394 0 419 L 0 016 0 050 0...

Page 189: ...60 1 75 53 63 69 A1 0 10 0 15 0 25 4 6 10 A2 1 50 59 b 0 20 0 254 0 30 8 10 12 b1 0 20 0 254 0 28 8 11 11 C 0 18 0 203 0 25 7 8 10 C1 0 18 0 203 0 23 7 8 9 D 8 56 8 66 8 74 337 341 344 E 5 80 6 00 6 2...

Page 190: ...n 12 bit ADC SONiX TECHNOLOGY CO LTD Page 190 Revision 1 93 S DIP28 PIN Symbols MIN NOR MAX A 0 210 A1 0 015 A2 0 114 0 130 0 135 D 1 390 1 390 1 400 E 0 310BSC E1 0 283 0 288 0 293 L 0 115 0 130 0 15...

Page 191: ...it micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 191 Revision 1 93 SOP28 PIN Symbols MIN MAX A 0 093 0 104 A1 0 004 0 012 D 0 697 0 713 E 0 291 0 299 H 0 394 0 419 L 0 016 0 050 0...

Page 192: ...700 A1 0 010 0 012 0 014 0 250 0 300 0 350 A2 0 075 0 079 0 087 1 900 2 000 2 200 b 0 012 0 300 C 0 004 0 006 0 008 0 100 0 150 0 200 D 0 512 0 520 0 528 13 000 13 200 13 400 D1 0 390 0 394 0 398 9 9...

Page 193: ...0 110 2 413 2 591 2 794 A1 0 008 0 012 0 016 0 203 0 305 0 406 A2 0 089 0 094 0 099 2 261 2 388 2 515 b 0 008 0 010 0 030 0 203 0 254 0 762 C 0 008 0 203 D 0 620 0 625 0 630 15 748 15 875 16 002 E 0...

Page 194: ...48 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 220 5 588 A1 0 015 0 381 A2 0 150 0 155 0 160 3 810 3 937 4 064 D 2 400 2 450 2 550 60 960 62 230 64 770 E 0 600 15 240 E1 0 540 0 545 0 550 13 716 1...

Page 195: ...40 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 220 5 588 A1 0 015 0 381 A2 0 150 0 115 0 160 3 810 2 921 4 064 D 2 055 2 060 2 070 52 197 52 324 52 578 E 0 600 15 240 E1 0 540 0 545 0 550 13 716 1...

Page 196: ...8P170X High_Clk 4M_X tal RC 12M_X tal High speed crystal 12M 32K_X tal Low speed crystal 32K Watch_Dog Enable Disable LVD Enable Disable Security Enable Disable High_Clk 2 Enable Disable OSG Enable Di...

Page 197: ...proved by OTP ICE ICE Version e g S8KD 2 6 Supply Voltage Volt High clock Hz 7 Code Option SN8P170X High_Clk 4M_X tal RC 12M_X tal High speed crystal 12M 32K_X tal Watch_Dog Enable Disable LVD Enable...

Page 198: ...or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affilia...

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