SONIX SN32F755, User Manual

Page: 63 / 225

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 63
Version 2.0
3.4.6 Divider Dividend register (SYS1_DIVIDEND)
Address Offset: 0x20
Bit Name Description Attribute Reset
31:0 Dividend[31:0]
Unsigned integer Dividend
R/W 0
3.4.7 Divider Divisor register (SYS1_DIVISOR)
Address Offset: 0x24

Note: Quotient is 0xFFFFFFFF when Divisor is 0x0, instead of occurring Hard Fault, since FW shall be
able to handle this case.
Bit Name Description Attribute Reset
31:0 Divisor[31:0]
Unsigned integer Divisor
R/W 0
3.4.8 Divider Quotient register (SYS1_QUOTIENT)
Address Offset: 0x28

Note: Quotient is 0xFFFFFFFF when Divisor is 0x0, instead of occurring Hard Fault, since FW shall be
able to handle this case.
Bit Name Description Attribute Reset
31:0 Quotient[31:0]
Unsigned integer Quotient
R/W 0
3.4.9 Divider Remainder register (SYS1_REMAINDER)
Address Offset: 0x2C
Bit Name Description Attribute Reset
31:0 Remainder[31:0]
Unsigned integer Remainder
R/W 0