SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 200
Version 2.0
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FLASH
17.1 OVERVIEW
SONiX 32-bit MCU integrated device feature in-system programmable (ISP) FLASH memory for convenient,
upgradeable code storage. The FLASH memory may be programmed via the SONiX 32-bit MCU programming
interface or by application code for maximum flexibility. SONiX 32-bit MCU provides security options at the disposal of
the designer to prevent unauthorized access to information stored in FLASH memory.
The MCU is stalled during Flash program and erase operations, although peripherals (Timers, WDT, I/O, PWM,
etc.) remain active.
Watchdog timer should be cleared if enabled before the Flash write or erase operation.
The erase operation sets all the bits in the Flash page to logic 1.
HW will hold system clock and automatically move out data from RAM and do programming, after programming
finished, HW will release system clock and let MCU execute the next instruction.
Note: HCLK
MUST be less or equal to 24MHz during Flash program and erase operations.
17.2 EMBEDDED FLASH MEMORY
The Flash memory is organized as 32-bit wide memory cells that can be used for storing both code and data constants,
and is located at a specific base address in the memory map of chip.
The high-performance Flash memory module in chip has the following key features:
Memory organization: the Flash memory is organized as a User ROM, Boot ROM.
User ROM
Up to 16K × 32 bits divided into 64 pages of 1024 Bytes
Boot ROM
Up to 1K × 32 bits divided into 4 pages of 1024 Bytes
The Flash interface implements instruction access and data access based on the AHB protocol. It implements the logic
necessary to carry out Flash memory operations (Program/Erase). Program/Erase operations can be performed over
the whole product voltage range.
17.3 FEATURES
Read interface (32-bit)
Flash Program / Erase operation
Code Option includes Code Security (CS)
Write operations to the main memory block and the code options are managed by an embedded Flash Memory
Controller (FMC). The high voltage needed for Program/Erase operations is internally generated. The main Flash
memory can be read/write protected against different levels of Code Security (CS).
During a write operation to the Flash memory, any attempt to read the Flash memory will stall the bus. The read
operation will proceed correctly once the write operation has completed. This means that code or data fetches cannot
be made while a write/erase operation is ongoing.
