SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 123
Version 1.1
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the CIS bits) is sampled on every
rising edge of the PCLK clock. After comparing two consecutive samples of this CAP input, one of the following four
events is recognized: rising edge, falling edge, either of edges or no changes in the level of the selected CAP input. Only
if the identified event occurs, and the event corresponds to the one selected by CTM bits in this register, will the Timer
Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising
edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input
cannot exceed one half of the PCLK clock. Consequently, the duration of the HIGH/LOW levels on the same CAP input
in this case cannot be shorter than 1/ (2 x PCLK).
Note: If Counter mode is selected in the CNTCTRL register, bit 2~0 of Capture Control (CAPCTRL) register
must be programmed as 0x0.
Bit
Name
Description
Attribute
Reset
31:2
Reserved
R
0
1:0
CTM[1:0]
Counter/Timer Mode.
This field selects which rising PCLK edges can
increment Timer’s Prescale
Counter (PC), or clear PC and increment Timer Counter (TC).
00: Timer Mode: every rising PCLK edge
01: Counter Mode: TC is incremented on rising edges on the CAP0 input
10: Counter Mode: TC is incremented on falling edges on the CAP0 input
11: Counter Mode: TC is incremented on both edges on the CAP0 input
R/W
0
10.8.8 CT16Bn Match Control register (CT16Bn_MCTRL) (n=0,2,5)
Address Offset: 0x14
Note: When the dead-band function is enabled in Center-aligned mode, and MR9RST=1, CT16Bn_PWMxN
will always output “0”
Note: When the dead-band function is enabled
- System will reset TC refer to MR9RST ONLY in Up-counting mode
- In Down counting mode, TC[15:0] will be reloaded from CT16Bn_MR9 after resetting counter
- System will reset TC refer to MR9RST ONLY in Center-aligned mode
Bit
Name
Description
Attribute
Reset
31:24
PWMKEY[7:0]
PWM register key.
Read as 0. When writing to the register you must write 0x5A to PWMKEY,
otherwise behaviour of writing to the register is ignored.
W
0
23
MR9STOP
Stop MR9: TC and PC will stop and CEN bit will be cleared if MR9 matches
TC.
0: Disable
1: Enable
R/W
0
22
MR9RST
Enable reset TC when MR9 matches TC.
0: Disable
1: Enable
R/W
0
21
MR9IE
Enable generating an interrupt based on CM[2:0] when MR9 matches the
value in the TC.
0: Disable
1: Enable
R/W
0
20:12
Reserved
R
0
11
MR3STOP
Stop MR3: TC and PC will stop and CEN bit will be cleared if MR3 matches
TC.
0: Disable
1: Enable
R/W
0
